发明授权
- 专利标题: Normally-off power JFET and manufacturing method thereof
- 专利标题(中): 常关断电源JFET及其制造方法
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申请号: US14536625申请日: 2014-11-09
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公开(公告)号: US09543395B2公开(公告)日: 2017-01-10
- 发明人: Koichi Arai , Yasuaki Kagotoshi , Nobuo Machida , Natsuki Yokoyama , Haruka Shimizu
- 申请人: Renesas Electronics Corporation
- 申请人地址: JP Tokyo
- 专利权人: Renesas Electronics Corporation
- 当前专利权人: Renesas Electronics Corporation
- 当前专利权人地址: JP Tokyo
- 代理机构: Shapiro, Gabor and Rosenberger, PLLC
- 优先权: JP2011-019438 20110201
- 主分类号: H01L29/10
- IPC分类号: H01L29/10 ; H01L29/16 ; H01L29/36 ; H01L29/04 ; H01L29/423 ; H01L29/66 ; H01L29/808
摘要:
In general, in a semiconductor active element such as a normally-off JFET based on SiC in which an impurity diffusion speed is significantly lower than in silicon, gate regions are formed through ion implantation into the side walls of trenches formed in source regions. However, to ensure the performance of the JFET, it is necessary to control the area between the gate regions thereof with high precision. Besides, there is such a problem that, since a heavily doped PN junction is formed by forming the gate regions in the source regions, an increase in junction current cannot be avoided. The present invention provides a normally-off power JFET and a manufacturing method thereof and forms the gate regions according to a multi-epitaxial method which repeats a process including epitaxial growth, ion implantation, and activation annealing a plurality of times.
公开/授权文献
- US20150060887A1 NORMALLY-OFF POWER JFET AND MANUFACTURING METHOD THEREOF 公开/授权日:2015-03-05
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