Invention Grant
- Patent Title: Chip package and manufacturing method thereof
- Patent Title (中): 芯片封装及其制造方法
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Application No.: US15138119Application Date: 2016-04-25
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Publication No.: US09548265B2Publication Date: 2017-01-17
- Inventor: Yen-Shih Ho , Shu-Ming Chang , Hsing-Lung Shen , Yu-Hao Su , Kuan-Jung Wu , Yi Cheng
- Applicant: XINTEC INC.
- Applicant Address: TW Taoyuan
- Assignee: XINTEC INC.
- Current Assignee: XINTEC INC.
- Current Assignee Address: TW Taoyuan
- Agency: Liu & Liu
- Priority: TW104126716A 20150817
- Main IPC: H01L23/495
- IPC: H01L23/495 ; H01L23/498 ; H01L21/48 ; H01L21/687 ; H01L49/02

Abstract:
A chip package includes a chip, an isolation layer, and a redistribution layer. The chip has a substrate, an electrical pad, and a protection layer. The substrate has a first surface and a second surface. The substrate has a through hole, and protection layer has a concave hole, such that the electrical pad is exposed through the concave hole and the through hole. The isolation layer is located on the second surface, the sidewall of the through hole, and the sidewall of the concave hole. The redistribution layer includes a connection portion and a passive element portion. The connection portion is located on isolation layer and in electrical contact with the electrical pad. The passive element portion is located on isolation layer that is on second surface, and an end of passive element portion is connected to connection portion that is on the second surface.
Public/Granted literature
- US20160315043A1 CHIP PACKAGE AND MANUFACTURING METHOD THEREOF Public/Granted day:2016-10-27
Information query
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