公开(公告)号：US12237354B2

公开(公告)日：2025-02-25

申请号：US17683917

申请日：2022-03-01

Applicant: XINTEC INC.

Inventor： Tsang-Yu Liu ,  Shu-Ming Chang ,  Chaung-Lin Lai

IPC: H01L27/146

Abstract: Chip packages and methods for forming the same are provided. The method includes providing a substrate having upper and lower surfaces, and having a chip region and a scribe-line region surrounding the chip region. The substrate has a dielectric layer on its upper surface. A masking layer is formed over the substrate to cover the dielectric layer. The masking layer has a first opening exposing the dielectric layer and extending in the extending direction of the scribe-line region to surround the chip region. An etching process is performed on the dielectric layer directly below the first opening, to form a second opening that is in the dielectric layer directly below the first opening. The masking layer is removed to expose the dielectric layer having the second opening. A dicing process is performed on the substrate through the second opening.

公开(公告)号：US09570398B2

公开(公告)日：2017-02-14

申请号：US13895219

申请日：2013-05-15

Applicant: XINTEC INC.

Inventor： Shu-Ming Chang ,  Yu-Ting Huang ,  Tsang-Yu Liu ,  Yen-Shih Ho

IPC: H01L23/538 ,  H01L21/78 ,  H01L23/48 ,  B81B7/00 ,  H01L23/00 ,  H01L21/683 ,  H01L23/60

CPC classification number: H01L23/5384 ,  B81B7/007 ,  B81B2207/095 ,  B81B2207/096 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/481 ,  H01L23/60 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/11 ,  H01L24/13 ,  H01L24/29 ,  H01L24/32 ,  H01L24/80 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2221/68381 ,  H01L2224/02331 ,  H01L2224/02371 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05617 ,  H01L2224/05624 ,  H01L2224/08147 ,  H01L2224/08148 ,  H01L2224/13021 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/8385 ,  H01L2224/92 ,  H01L2224/94 ,  H01L2924/10155 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/01032 ,  H01L2224/80 ,  H01L2224/83 ,  H01L21/304 ,  H01L21/76898 ,  H01L2221/68304 ,  H01L2224/0231 ,  H01L2224/11

Abstract: An embodiment of the invention provides a chip package which includes: a first substrate; a second substrate disposed thereon, wherein the second substrate includes a lower semiconductor layer, an upper semiconductor layer, and an insulating layer therebetween, and a portion of the lower semiconductor layer electrically contacts with at least one pad on the first substrate; a conducting layer disposed on the upper semiconductor layer of the second substrate and electrically connected to the portion of the lower semiconductor layer electrically contacting with the at least one pad; an opening extending from the upper semiconductor layer towards the lower semiconductor layer and extending into the lower semiconductor layer; and a protection layer disposed on the upper semiconductor layer and the conducting layer, wherein the protection layer extends onto a portion of a sidewall of the opening, and does not cover the lower semiconductor layer in the opening.

Abstract translation: 本发明的实施例提供一种芯片封装，其包括：第一基板; 设置在其上的第二基板，其中所述第二基板包括下半导体层，上半导体层和绝缘层，并且所述下半导体层的一部分与所述第一基板上的至少一个焊盘电接触; 导电层，其设置在所述第二基板的所述上半导体层上并电连接到所述下半导体层与所述至少一个焊盘电接触的部分; 从上半导体层向下半导体层延伸并延伸到下半导体层的开口; 以及设置在所述上​​半导体层和所述导电层上的保护层，其中所述保护层延伸到所述开口的侧壁的一部分上，并且不覆盖所述开口中的下半导体层。

公开(公告)号：US20160240520A1

公开(公告)日：2016-08-18

申请号：US15007124

申请日：2016-01-26

Applicant: XINTEC INC.

Inventor： Yen-Shih Ho ,  Shu-Ming Chang ,  Hsing-Lung Shen

IPC: H01L25/16 ,  H01L21/304 ,  H01L21/78 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L25/16 ,  H01L21/486 ,  H01L23/291 ,  H01L23/293 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49894 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/94 ,  H01L2224/0233 ,  H01L2224/0236 ,  H01L2224/02375 ,  H01L2224/024 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/16055 ,  H01L2224/16057 ,  H01L2224/16225 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/05032 ,  H01L2924/19011 ,  H01L2924/19042 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/014

Abstract: A chip package includes a chip, a dielectric bonding layer, a carrier, and a redistribution layer. The chip has a substrate, a conductive pad, and a protection layer. The dielectric bonding layer is located on the protection layer and between the carrier and the protection layer. The carrier, the dielectric bonding layer, and the protection layer have a communicated through hole configured to expose the conductive pad. The redistribution layer includes a connection portion and a passive component portion. The connection portion is located on the conductive pad, the sidewall of the through hole, and a surface of the carrier facing away from the dielectric bonding layer. The passive component portion is located on the surface of the carrier, and an end of the passive component portion is connected to the connection portion that is on the surface of the carrier.

Abstract translation: 芯片封装包括芯片，电介质结合层，载体和再分配层。 芯片具有基板，导电焊盘和保护层。 电介质接合层位于保护层上，载体和保护层之间。 载体，介电接合层和保护层具有被配置为暴露导电垫的连通通孔。 再分配层包括连接部分和无源部件部分。 连接部分位于导电垫上，通孔的侧壁和载体的表面背离电介质结合层。 无源部件位于载体的表面上，无源部件的一端与载体表面上的连接部分连接。

公开(公告)号：US09054114B2

公开(公告)日：2015-06-09

申请号：US14290638

申请日：2014-05-29

Applicant: XINTEC INC.

Inventor： Hung-Jen Lee ,  Shu-Ming Chang ,  Chen-Han Chiang ,  Tsang-Yu Liu ,  Yen-Shih Ho

IPC: H01L23/544 ,  H01L21/56 ,  H01L23/16 ,  H01L23/31 ,  H01L23/00 ,  H01L21/683 ,  H01L23/498

CPC classification number: H01L23/544 ,  H01L21/561 ,  H01L21/6836 ,  H01L23/16 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/562 ,  H01L24/13 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2221/68377 ,  H01L2223/5446 ,  H01L2224/02377 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/131 ,  H01L2224/29011 ,  H01L2224/29013 ,  H01L2224/29124 ,  H01L2224/2957 ,  H01L2224/296 ,  H01L2224/3003 ,  H01L2224/30155 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2224/83125 ,  H01L2224/83127 ,  H01L2224/83192 ,  H01L2224/83895 ,  H01L2224/94 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/1461 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2224/83 ,  H01L2924/00014 ,  H01L2924/01032 ,  H01L2924/00

Abstract: An embodiment of the present invention provides a manufacturing method of a chip package structure including: providing a first substrate having a plurality of predetermined scribe lines defined thereon, wherein the predetermined scribe lines define a plurality of device regions; bonding a second substrate to the first substrate, wherein a spacing layer is disposed therebetween and has a plurality of chip support rings located in the device regions respectively and a cutting support structure located on peripheries of the chip support rings, and the spacing layer has a gap pattern separating the cutting support structure from the chip support rings; and cutting the first substrate and the second substrate to form a plurality of chip packages. Another embodiment of the present invention provides a chip package structure.

Abstract translation: 本发明的一个实施例提供了一种芯片封装结构的制造方法，包括：提供具有限定在其上的多个预定划线的第一基板，其中，所述预定划线限定多个器件区域; 将第二基板接合到第一基板，其中间隔层设置在其间并且分别具有位于装置区域中的多个芯片支撑环和位于芯片支撑环的周边的切割支撑结构，并且间隔层具有 将切割支撑结构与芯片支撑环分离的间隙图案; 以及切割所述第一基板和所述第二基板以形成多个芯片封装。 本发明的另一实施例提供一种芯片封装结构。

公开(公告)号：US08900924B2

公开(公告)日：2014-12-02

申请号：US14173340

申请日：2014-02-05

Applicant: Xintec Inc.

Inventor： Shu-Ming Chang ,  Tsang-Yu Liu ,  Yen-Shih Ho

IPC: H01L25/00 ,  H01L21/822 ,  B81C1/00 ,  H01L21/768 ,  H01L23/10 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L25/50 ,  B81C1/00238 ,  B81C2203/0785 ,  B81C2203/0792 ,  H01L21/76898 ,  H01L21/8221 ,  H01L23/10 ,  H01L24/05 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/73 ,  H01L24/94 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05554 ,  H01L2224/05567 ,  H01L2224/056 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05669 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/14517 ,  H01L2224/17517 ,  H01L2224/73103 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/05552

Abstract: An embodiment of the invention provides a chip package which includes: a first chip; a second chip disposed on the first chip; a hole extending from a surface of the first chip towards the second chip; a conducting layer disposed on the surface of the first chip and extending into the hole and electrically connected to a conducting region or a doped region in the first chip; and a support bulk disposed between the first chip and the second chip, wherein the support bulk substantially and/or completely covers a bottom of the hole.

Abstract translation: 本发明的实施例提供一种芯片封装，其包括：第一芯片; 设置在第一芯片上的第二芯片; 从所述第一芯片的表面向所述第二芯片延伸的孔; 导电层，设置在所述第一芯片的表面上并延伸到所述孔中并电连接到所述第一芯片中的导电区域或掺杂区域; 以及设置在所述第一芯片和所述第二芯片之间的支撑体，其中所述支撑体基本上和/或完全覆盖所述孔的底部。

公开(公告)号：US11164853B1

公开(公告)日：2021-11-02

申请号：US17170482

申请日：2021-02-08

Applicant: XINTEC INC.

Inventor： Chia-Ming Cheng ,  Shu-Ming Chang

IPC: H01L23/495 ,  H01L25/16 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00 ,  B81B7/00

Abstract: A chip package includes a first chip, a second chip, a first molding compound, and a first distribution line. The second chip vertically or laterally overlaps the first chip. The second chip has a conductive pad. The first molding compound covers the first and second chips, and surrounds the second chip. The first molding compound has a first through hole. The conductive pad is in the first through hole. The first distribution line is located on a surface of the first molding compound facing away from the second chip, and electrically connects the conductive pad in the first through hole.

公开(公告)号：US09881889B2

公开(公告)日：2018-01-30

申请号：US14251470

申请日：2014-04-11

Applicant: XINTEC INC.

Inventor： Yu-Lung Huang ,  Shu-Ming Chang ,  Tsang-Yu Liu ,  Yen-Shih Ho

IPC: H01L23/48 ,  H01L23/00 ,  H01L21/78 ,  H01L21/66

CPC classification number: H01L24/14 ,  H01L21/78 ,  H01L22/12 ,  H01L22/20 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L2224/11334 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2224/141 ,  H01L2224/14131 ,  H01L2224/14145 ,  H01L2224/14177 ,  H01L2224/14179 ,  H01L2224/16058 ,  H01L2224/16227 ,  H01L2224/17051 ,  H01L2224/17517 ,  H01L2224/17519 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/81986 ,  H01L2224/92 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/01322 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2224/14146 ,  H01L2224/81 ,  H01L2224/81907 ,  H01L2924/00012 ,  H01L2224/11

Abstract: A chip package is provided, in which includes: a packaging substrate, a chip and a plurality solder balls interposed between the packaging substrate and the chip for bonding the packaging substrate and the chip, wherein the solder balls include a first portion of a first size and a second portion of a second size that is different from the first size.

公开(公告)号：US09548265B2

公开(公告)日：2017-01-17

申请号：US15138119

申请日：2016-04-25

Applicant: XINTEC INC.

Inventor： Yen-Shih Ho ,  Shu-Ming Chang ,  Hsing-Lung Shen ,  Yu-Hao Su ,  Kuan-Jung Wu ,  Yi Cheng

IPC: H01L23/495 ,  H01L23/498 ,  H01L21/48 ,  H01L21/687 ,  H01L49/02

CPC classification number: H01L23/49838 ,  C25D17/001 ,  C25D17/005 ,  C25D17/06 ,  H01L21/2885 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/68721 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/498 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/5227 ,  H01L23/525 ,  H01L23/53214 ,  H01L23/53228 ,  H01L28/10 ,  H01L2224/11

Abstract: A chip package includes a chip, an isolation layer, and a redistribution layer. The chip has a substrate, an electrical pad, and a protection layer. The substrate has a first surface and a second surface. The substrate has a through hole, and protection layer has a concave hole, such that the electrical pad is exposed through the concave hole and the through hole. The isolation layer is located on the second surface, the sidewall of the through hole, and the sidewall of the concave hole. The redistribution layer includes a connection portion and a passive element portion. The connection portion is located on isolation layer and in electrical contact with the electrical pad. The passive element portion is located on isolation layer that is on second surface, and an end of passive element portion is connected to connection portion that is on the second surface.

Abstract translation: 芯片封装包括芯片，隔离层和再分配层。 芯片具有基板，电焊盘和保护层。 基板具有第一表面和第二表面。 基板具有通孔，保护层具有凹孔，使得电焊盘通过凹孔和通孔露出。 隔离层位于第二表面，通孔的侧壁和凹孔的侧壁上。 再分配层包括连接部分和无源元件部分。 连接部分位于隔离层上并与电焊垫电接触。 无源元件部分位于第二表面上的隔离层上，无源元件部分的一端连接到第二表面上的连接部分。

公开(公告)号：US09373597B2

公开(公告)日：2016-06-21

申请号：US14662151

申请日：2015-03-18

Applicant: XINTEC INC.

Inventor： Yen-Shih Ho ,  Chia-Ming Cheng ,  Shu-Ming Chang

IPC: H01L23/00 ,  H01L29/06 ,  H01L23/525

CPC classification number: H01L24/14 ,  H01L23/525 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L29/0657 ,  H01L2224/02233 ,  H01L2224/02313 ,  H01L2224/0235 ,  H01L2224/0236 ,  H01L2224/0237 ,  H01L2224/02371 ,  H01L2224/02375 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/14155 ,  H01L2224/14165 ,  H01L2924/014 ,  H01L2924/01029 ,  H01L2924/01013 ,  H01L2924/00014

Abstract: The present invention provides a chip package that includes a semiconductor chip, at least one recess, a plurality of first redistribution metal lines, and at least one protrusion. The semiconductor chip has a plurality of conductive pads disposed on an upper surface of the semiconductor chip. The recess extends from the upper surface to a lower surface of the semiconductor chip, and is arranged on the side of the semiconductor chip. The first redistribution metal lines are disposed on the upper surface, electrically connected to the conductive pad individually, and extended into the recesses separately. The protrusion is disposed in the recess and located between the adjacent first redistribution metal lines.

Abstract translation: 本发明提供了一种芯片封装，其包括半导体芯片，至少一个凹槽，多个第一再分布金属线以及至少一个突起。 半导体芯片具有设置在半导体芯片的上表面上的多个导电焊盘。 凹部从半导体芯片的上表面延伸到下表面，并且布置在半导体芯片的侧面上。 第一再分布金属线设置在上表面上，分别电连接到导电垫，并分别延伸到凹槽中。 突出部设置在凹部中并且位于相邻的第一再分布金属线之间。

公开(公告)号：US09275963B2

公开(公告)日：2016-03-01

申请号：US14199640

申请日：2014-03-06

Applicant: XINTEC INC.

Inventor： Yung-Tai Tsai ,  Shu-Ming Chang ,  Chun-Wei Chang ,  Chien-Hui Chen ,  Tsang-Yu Liu ,  Yen-Shih Ho

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/78

CPC classification number: H01L24/05 ,  H01L21/78 ,  H01L23/3185 ,  H01L23/3192 ,  H01L24/03 ,  H01L2224/02371 ,  H01L2224/04042 ,  H01L2224/05124 ,  H01L2224/05548 ,  H01L2224/05568 ,  H01L2224/05624 ,  H01L2224/94 ,  H01L2924/10156 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2224/03 ,  H01L2924/00014

Abstract: A semiconductor structure includes a wafer, at least one nonmetal oxide layer, a pad, a passivation layer, an isolation layer, and a conductive layer. The wafer has a first surface, a second surface, a third surface, a first stage difference surface connected between the second and third surfaces, and a second stage difference surface connected between the first and third surfaces. The nonmetal oxide layer is located on the first surface of the wafer. The pad is located on the nonmetal oxide layer and electrically connected to the wafer. The passivation layer is located on the nonmetal oxide layer. The isolation layer is located on the passivation layer, nonmetal oxide layer, the first, second and third surfaces of the wafer, and the first and second stage difference surfaces of the wafer. The conductive layer is located on the isolation layer and electrically contacts the pad.

Abstract translation: 半导体结构包括晶片，至少一个非金属氧化物层，焊盘，钝化层，隔离层和导电层。 晶片具有连接在第二和第三表面之间的第一表面，第二表面，第三表面，第一阶段差异表面以及连接在第一和第三表面之间的第二阶段差异表面。 非金属氧化物层位于晶片的第一表面上。 垫位于非金属氧化物层上并电连接到晶片。 钝化层位于非金属氧化物层上。 隔离层位于钝化层，非金属氧化物层，晶片的第一，第二和第三表面以及晶片的第一和第二级差分表面上。 导电层位于隔离层上并电接触焊盘。