Invention Grant
- Patent Title: Doped metal-insulator-transition latch circuitry
- Patent Title (中): 掺杂的金属 - 绝缘体转换锁存电路
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Application No.: US14534205Application Date: 2014-11-06
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Publication No.: US09552852B2Publication Date: 2017-01-24
- Inventor: Brent A. Anderson , Kota V. R. M. Murali , Edward J. Nowak
- Applicant: GLOBALFOUNDRIES INC.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES INC.
- Current Assignee: GLOBALFOUNDRIES INC.
- Current Assignee Address: KY Grand Cayman
- Agent Anthony J. Canale
- Main IPC: H01L45/00
- IPC: H01L45/00 ; H01L27/105 ; G11C7/10 ; H01L21/768 ; H03K5/13 ; H01L27/24 ; G11C7/02

Abstract:
Some embodiments of the present invention may include one, or more, of the following features, characteristics or advantages: (i) latch device including multiple Ecrit material regions all electrically connected to a common terminal (sometimes structured and shaped in the form of a storage plate conductor); (ii) bi-stable three-terminal latch device using two Ecrit property regions; (iii) three-terminal, two-Ecrit-region latch device where, for each Ecrit region, (Vdd−Vss) divided by (region thickness, dn) is greater than the region's Ecrit value; or (iv) use of multiple Ecrit material region latch devices to provide data storage instrumentality in a static memory device.
Public/Granted literature
- US20160133303A1 DOPED METAL-INSULATOR-TRANSITION LATCH CIRCUITRY Public/Granted day:2016-05-12
Information query
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