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    Simplified memory cells based on fully-depleted silicon-on-insulator transistors
    1.
    发明授权
    Simplified memory cells based on fully-depleted silicon-on-insulator transistors 有权

    公开(公告)号：US10727253B1

    公开(公告)日：2020-07-28

    申请号：US16266307

    申请日：2019-02-04

    申请人： GLOBALFOUNDRIES Inc.

    发明人： Edward J. Nowak

    IPC分类号： H01L21/00 ,  H01L27/12 ,  H01L21/84 ,  H01L21/762

    摘要： Structures for a memory cell and methods associated with forming and using such structures. The structure includes a silicon-on-insulator wafer including a device layer, a substrate, and a buried insulator layer between the device layer and the substrate. The structure further includes a field-effect transistor having first and second source/drain regions and a gate electrode that are over the buried insulator layer. A moat region is arranged in the substrate beneath the field-effect transistor, a well is arranged in the substrate beneath the moat region, and an isolation region extends through the device layer and the buried insulator layer into the substrate. The isolation region is arranged to surround a portion of the device layer defining an active region for the field-effect transistor and a portion of the moat region. A fence region, which extends between the well and the isolation region, surrounds the portion of the moat region.

    VERTICAL FIELD EFFECT TRANSISTORS INCORPORATING U-SHAPED SEMICONDUCTOR BODIES AND METHODS
    2.
    发明申请
    VERTICAL FIELD EFFECT TRANSISTORS INCORPORATING U-SHAPED SEMICONDUCTOR BODIES AND METHODS 审中-公开

    公开(公告)号：US20190287863A1

    公开(公告)日：2019-09-19

    申请号：US15920748

    申请日：2018-03-14

    申请人： GLOBALFOUNDRIES INC.

    发明人： Ruilong Xie ,  Lars Liebmann ,  Edward J. Nowak ,  Julien Frougier ,  Jia Zeng

    IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/02

    摘要： Disclosed is a semiconductor structure that includes a vertical field effect transistor (VFET) with a U-shaped semiconductor body. The semiconductor structure can be a standard VFET or a feedback VFET. In either case, the VFET includes a lower source/drain region, a semiconductor body on the lower source/drain region, and an upper source/drain region on the top of the semiconductor body. Rather than having an elongated fin shape, the semiconductor body folds back on itself in the Z direction so as to be essentially U-shaped (as viewed from above). Using a U-shaped semiconductor body reduces the dimension of the VFET in the Z direction without reducing the end-to-end length of the semiconductor body. Thus, VFET cell height can be reduced without reducing device drive current or violating critical design rules. Also disclosed is a method of forming a semiconductor structure that includes such a VFET with a U-shaped semiconductor body.

    Vertical transistors and methods of forming same
    3.
    发明授权
    Vertical transistors and methods of forming same 有权

    公开(公告)号：US10256235B2

    公开(公告)日：2019-04-09

    申请号：US15893860

    申请日：2018-02-12

    申请人： GLOBALFOUNDRIES INC.

    发明人： Brent A. Anderson ,  Edward J. Nowak

    IPC分类号： H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L29/10

    摘要： One aspect of the disclosure relates to an integrated circuit structure. The integrated circuit structure may include a fin having a first source/drain region and a second source/drain, the first source/drain region being over a substrate and below a central region of the fin, and the second source/drain region being within a dielectric layer and over the central region of the fin; a gate structure within the dielectric layer substantially surrounding the central region of the fin between the first source/drain region and the second source drain region, wherein the fin includes at least one tapered region from the central region of the fin to at least one of the first source/drain region or the second source/drain region.

    Interconnects for vertical-transport field-effect transistors
    4.
    发明授权
    Interconnects for vertical-transport field-effect transistors 有权

    公开(公告)号：US09887192B2

    公开(公告)日：2018-02-06

    申请号：US15198044

    申请日：2016-06-30

    申请人： GLOBALFOUNDRIES Inc.

    发明人： Edward J. Nowak ,  Brent A. Anderson

    IPC分类号： H01L29/66 ,  H01L27/088 ,  H01L29/78 ,  H01L29/08 ,  H01L21/8234

    CPC分类号： H01L27/088 ,  H01L21/823475 ,  H01L29/0847 ,  H01L29/66666 ,  H01L29/7827

    摘要： Structures and fabrication methods for vertical-transport field-effect transistors. The structure includes a vertical-transport field-effect transistor having a source/drain region located in a semiconductor layer, a fin projecting from the source/drain region in the semiconductor layer, and a gate electrode on the semiconductor layer and coupled with the fin. The structure further includes an interconnect located in a trench defined in the semiconductor layer. The interconnect is coupled with the source/drain region or the gate electrode of the vertical-transport field-effect transistor, and may be used to couple the source/drain region or the gate electrode of the vertical-transport field-effect transistor with a source/drain region or a gate electrode of another vertical-transport field-effect transistor.

    Dielectric filler fins for planar topography in gate level
    8.
    发明授权
    Dielectric filler fins for planar topography in gate level 有权

    公开(公告)号：US09245981B2

    公开(公告)日：2016-01-26

    申请号：US14808914

    申请日：2015-07-24

    申请人： GLOBALFOUNDRIES INC.

    发明人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Bruce B. Doris ,  Ali Khakifirooz ,  Edward J. Nowak ,  Kern Rim

    IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/06

    CPC分类号： H01L29/66795 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/785

    摘要： An array of stacks containing a semiconductor fins and an oxygen-impermeable cap is formed on a semiconductor substrate with a substantially uniform areal density. Oxygen-impermeable spacers are formed around each stack, and the semiconductor substrate is etched to vertically extend trenches. Semiconductor sidewalls are physically exposed from underneath the oxygen-impermeable spacers. The oxygen-impermeable spacers are removed in regions in which semiconductor fins are not needed. A dielectric oxide material is deposited to fill the trenches. Oxidation is performed to convert a top portion of the semiconductor substrate and semiconductor fins not protected by oxygen-impermeable spacers into dielectric material portions. Upon removal of the oxygen-impermeable caps and remaining oxygen-impermeable spacers, an array including semiconductor fins and dielectric fins is provided. The dielectric fins alleviate variations in the local density of protruding structures, thereby reducing topographical variations in the height of gate level structures to be subsequently formed.