Invention Grant
US09553047B2 Method of manufacturing semiconductor devices with combined array and periphery patterning in self-aligned quadruple patterning
有权
在自对准四重图案化中制造具有组合阵列和周边图案的半导体器件的方法
- Patent Title: Method of manufacturing semiconductor devices with combined array and periphery patterning in self-aligned quadruple patterning
- Patent Title (中): 在自对准四重图案化中制造具有组合阵列和周边图案的半导体器件的方法
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Application No.: US14735790Application Date: 2015-06-10
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Publication No.: US09553047B2Publication Date: 2017-01-24
- Inventor: Yu-Min Hung , Tzung-Ting Han , Miao-Chih Hsu
- Applicant: Macronix International Co. Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Macronix International Co., Ltd.
- Current Assignee: Macronix International Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Alston & Bird LLP
- Main IPC: H01L23/528
- IPC: H01L23/528 ; H01L21/768 ; H01L21/3213 ; H01L27/112
Abstract:
Provided are improved semiconductor memory devices and methods for manufacturing such semiconductor memory devices. A method may incorporate the patterning of the array and periphery regions in self-aligned quadruple patterning and provide semiconductor devices resulting from the combined patterning.
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