Invention Grant
- Patent Title: Methods and arrangements for a check sequence
- Patent Title (中): 检查顺序的方法和布置
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Application No.: US13725693Application Date: 2012-12-21
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Publication No.: US09559810B2Publication Date: 2017-01-31
- Inventor: Thomas Tetzlaff , Minyoung Park
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwegman Lundberg & Woessner, P.A.
- Main IPC: H04L1/00
- IPC: H04L1/00

Abstract:
According to various aspects of the present disclosure, medium access control (MAC) sublayer logic of a device or a system may generate and implement a preamble structure of a data unit including a signal field which includes a four-bit cyclic redundancy check sequence providing a Hamming distance of two. The signal field portion of the preamble structure may include information related to a plurality of physical layer parameters used for wireless communication of the data unit. The preamble structure may be stored on a machine-accessible medium. The preamble may be generated by a data unit builder of the device, which may further receive a frame including a data payload, and encapsulate the frame with the preamble portion to generate the data unit. A transmitter coupled with the data unit builder may then wirelessly transmit the data unit using an antenna array.
Public/Granted literature
- US20140071996A1 METHODS AND ARRANGEMENTS FOR A CHECK SEQUENCE Public/Granted day:2014-03-13
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