Invention Grant
US09562946B2 Integrated circuit wafer having plural dies with each die including test circuit receiving expected data and mask data from different pads 有权
具有多个管芯的集成电路晶片,每个管芯包括测试电路接收来自不同焊盘的预期数据和掩模数据

Integrated circuit wafer having plural dies with each die including test circuit receiving expected data and mask data from different pads
Abstract:
Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the plurality of die/ICs. The response patterns from the tester are input to the test circuits along with the output response of the die/IC to be compared. Also disclosed is the use of a response signal encoding scheme whereby the tester transmits response test commands to the test circuits, using a single signal per test circuit, to perform: (1) a compare die/IC output against an expected logic high, (2) a compare die/IC output against an expected logic low, and (3) a mask compare operation. The use of the signal encoding scheme allows functional testing of die and ICs since all response test commands (i.e. 1-3 above) required at each die/IC output can be transmitted to each die/IC output using only a single tester signal connection per die/IC output. In addition to functional testing, scan testing of die and ICs is also possible.
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