发明授权
US09563737B1 Method, system, and computer program product for checking or verifying shapes in track patterns for electronic circuit designs
有权
用于检查或验证电子电路设计的轨迹图案形状的方法,系统和计算机程序产品
- 专利标题: Method, system, and computer program product for checking or verifying shapes in track patterns for electronic circuit designs
- 专利标题(中): 用于检查或验证电子电路设计的轨迹图案形状的方法,系统和计算机程序产品
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申请号: US14318488申请日: 2014-06-27
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公开(公告)号: US09563737B1公开(公告)日: 2017-02-07
- 发明人: Alexandre Arkhipov , Jeffrey Markham , Karun Sharma
- 申请人: Cadence Design Systems, Inc.
- 申请人地址: US CA San Jose
- 专利权人: Cadence Design Systems, Inc.
- 当前专利权人: Cadence Design Systems, Inc.
- 当前专利权人地址: US CA San Jose
- 代理机构: Vista IP Law Group, LLP
- 主分类号: G06F9/455
- IPC分类号: G06F9/455 ; G06F17/50
摘要:
Methods and systems for checking or verifying shapes in electronic designs are disclosed. The method identifies a dictionary (if pre-existing) or determining the dictionary by creating the dictionary and reduces dimensionality of design data by using a sliced line. Shapes are transformed into sliced line segments along the sliced line. Dictionary entries for shapes are associated with corresponding sliced line segments, and the design is checked or verified using the sliced line segments and the associated dictionary entries rather than using two-dimensional shapes or geometric data. Sliced line segments may be further partitioned or merged. Non-conforming shapes corresponding to no tracks of track patterns are identified and determined whether violations of design rules or requirements may be resolved by one or more other shapes using the corresponding sliced line segments.
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