公开(公告)号：US09396301B1

公开(公告)日：2016-07-19

申请号：US14292166

申请日：2014-05-30

Applicant: Cadence Design Systems, Inc.

Inventor： Yinnie Lee ,  Jeffrey Markham ,  Roland Ruehl ,  Karun Sharma

IPC: G06F17/50

CPC classification number: G06F17/5077

Abstract: Methods and systems for interconnecting circuit components with track patterns are disclosed. The method identifies a source pin on a first track and a destination pin on a second track and determines a third track in a different routing direction based on design rules governing track patterns. The method further determines a transition pattern for the interconnection between the source pin and the destination pin by using at least the third track. The method may use one or more dummy pins or ordering of pin connections in implementing the interconnection to satisfy certain design rules. The lengths of some wire segments of the interconnection may be further adjusted to satisfy certain design rules. Compaction may be performed to have two wire segments share the same track while the lengths or widths of one or both wire segments may be further modified to ensure design rule compliance.

Abstract translation: 公开了用于将具有轨迹图案的电路组件互连的方法和系统。 该方法基于管理轨迹图案的设计规则，识别第二轨道上的第一轨道和目的地针脚上的源极引脚，并确定不同路线方向上的第三轨道。 该方法通过使用至少第三个轨道来确定源极引脚和目标引脚之间的互连的转换模式。 该方法可以使用一个或多个虚拟引脚或引脚连接的顺序来实现互连以满足某些设计规则。 可以进一步调整互连的一些线段的长度以满足某些设计规则。 可以执行压实以使两个线段共享相同的轨道，同时可以进一步修改一个或两个线段的长度或宽度以确保设计规则符合性。

公开(公告)号：US08719765B2

公开(公告)日：2014-05-06

申请号：US13797788

申请日：2013-03-12

Applicant: Cadence Design Systems, Inc.

Inventor： Min Cao ,  Jeffrey Markham

IPC: G06F17/50

CPC classification number: G06F17/50 ,  G03F1/68 ,  G03F1/70

Abstract: A hierarchical schematic design editor displays mask layers for each shape as mask specific colors and alerts a user to mask layer conflicts during the design and editing process. According to an embodiment, mask colors may be assigned at the time the shapes or geometries and cells are placed in a circuit design layout, or when a mask layer condition indicating that two or more shapes should be set to different mask layers is detected. In an embodiment, if the distance between two shapes is less than a predetermined threshold, those shapes may cause a mask layer condition. Shapes may be grouped to facilitate mask layer condition detection and mask layer assignment.

Abstract translation: 分层示意图设计编辑器将每个形状的掩模层显示为掩模特定颜色，并提醒用户在设计和编辑过程中屏蔽层冲突。 根据实施例，可以在形状或几何形状和单元被放置在电路设计布局中时，或者当指示将两个或多个形状设置为不同掩模层的掩模层条件时，可以分配掩模颜色。 在一个实施例中，如果两个形状之间的距离小于预定阈值，则这些形状可能导致掩模层条件。 形状可以被分组以便于掩模层条件检测和掩模层分配。

公开(公告)号：US10296695B1

公开(公告)日：2019-05-21

申请号：US14292067

申请日：2014-05-30

Applicant: Cadence Design Systems, Inc.

Inventor： Yinnie Lee ,  Jeffrey Markham ,  Roland Ruehl ,  Karun Sharma

IPC: G06F17/50

Abstract: Methods and systems for implementing track pattern for electronic designs are disclosed. The method identifies a first track in a design and viable implementing options for the first track. When adding a second track to the track pattern, the method determines whether the second track corresponds to the viable implementing options for the track. The second track is inserted to the track pattern and situated immediately adjacent to the first track if the second track is determined to correspond to a viable implementing option for the first track. One or more intermediate tracks may be inserted immediately adjacent to the first track before inserting the second track to produce a legal track pattern. Tracks may be removed from a track pattern. One or more intermediate tracks may be inserted into the space occupied by a track being removed to ensure track pattern's compliance with design rules after the track removal.

公开(公告)号：US10049175B1

公开(公告)日：2018-08-14

申请号：US14800596

申请日：2015-07-15

Applicant: Cadence Design Systems, Inc.

Inventor： Jeffrey S. Salowe ,  Min Cao ,  Roland Ruehl ,  Jeffrey Markham

IPC: G06F17/50

Abstract: Some aspects enable users to interactively define a region in an electronic design, identify or generate a track pattern, and assign the track pattern to the region for subsequent physical implementation for the region. Another aspect interactively represents various results on a display apparatus using one or more distinguishing representation schemes. Another aspect is directed at interactive editing a component of an electronic design having track patterns by iteratively modifying a set of track patterns to reach a reduced set of track patterns and by automatically snapping the component to active track(s) in the reduced set for the physical implementation.

公开(公告)号：US09563737B1

公开(公告)日：2017-02-07

申请号：US14318488

申请日：2014-06-27

Applicant: Cadence Design Systems, Inc.

Inventor： Alexandre Arkhipov ,  Jeffrey Markham ,  Karun Sharma

IPC: G06F9/455 ,  G06F17/50

CPC classification number: G06F17/5081

Abstract: Methods and systems for checking or verifying shapes in electronic designs are disclosed. The method identifies a dictionary (if pre-existing) or determining the dictionary by creating the dictionary and reduces dimensionality of design data by using a sliced line. Shapes are transformed into sliced line segments along the sliced line. Dictionary entries for shapes are associated with corresponding sliced line segments, and the design is checked or verified using the sliced line segments and the associated dictionary entries rather than using two-dimensional shapes or geometric data. Sliced line segments may be further partitioned or merged. Non-conforming shapes corresponding to no tracks of track patterns are identified and determined whether violations of design rules or requirements may be resolved by one or more other shapes using the corresponding sliced line segments.

Abstract translation: 公开了用于检查或验证电子设计中的形状的方法和系统。 该方法识别字典（如果已经存在）或通过创建字典来确定字典，并通过使用切片线来减少设计数据的维度。 形状沿切片线转换成切片线段。 形状的词典条目与对应的切片线段相关联，并且使用切片线段和相关联的词典条目来检查或验证设计，而不是使用二维形状或几何数据。 切片线段可进一步分割或合并。 识别和确定对应于轨道图案的轨迹的不一致形状，可以使用相应的切片线段通过一个或多个其它形状来解决违反设计规则或要求的情况。

公开(公告)号：US09117052B1

公开(公告)日：2015-08-25

申请号：US13931568

申请日：2013-06-28

Applicant: Cadence Design Systems, Inc.

Inventor： Jeffrey Salowe ,  Min Cao ,  Roland Ruehl ,  Jeffrey Markham

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5068 ,  G06F17/5077 ,  G06F17/5081

Abstract: Some aspects enable users to interactively define a region in an electronic design, identify or generate a track pattern, and assign the track pattern to the region for subsequent physical implementation for the region. Another aspect interactively represents various results on a display apparatus using one or more distinguishing representation schemes. Another aspect is directed at interactive editing a component of an electronic design having track patterns by iteratively modifying a set of track patterns to reach a reduced set of track patterns and by automatically snapping the component to active track(s) in the reduced set for the physical implementation.

Abstract translation: 一些方面使得用户能够交互地定义电子设计中的区域，识别或生成轨迹图案，并将轨迹图案分配给该区域以用于该区域的后续物理实施。 另一方面交互地表示使用一个或多个区分表示方案的显示设备上的各种结果。 另一方面涉及通过迭代地修改一组轨道图案以达到减少的一组轨道图案并且通过将该组件自动地捕捉到该缩减集中的主动轨迹来交互编辑具有轨道图案的电子设计的组件， 物理实现。

公开(公告)号：US09372955B1

公开(公告)日：2016-06-21

申请号：US14292122

申请日：2014-05-30

Applicant: Cadence Design Systems, Inc.

Inventor： Yinnie Lee ,  Jeffrey Markham ,  Roland Ruehl ,  Karun Sharma

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5077

Abstract: Methods and systems for implementing repetitive track patterns for electronic designs are disclosed. The method determines a track pattern within a period and repeats the track pattern for a number of times to form repetitive track patterns. Compliance with photomask designation design rules and track pattern design rules by both the track pattern and the repetitive track patterns is maintained by adding one or more intermediate tracks. A track may be added or removed from the track pattern or replaced by another track associated with a different width by using one or more intermediate tracks. The method may validate a period and replace an invalid period with a valid period. During the identification of the tracks in a track pattern for constructing repetitive track patterns, the method also forward predicts a predetermined number of tracks or predicts one or more tracks for a predetermined distance.

Abstract translation: 公开了用于实现电子设计的重复轨迹模式的方法和系统。 该方法确定一段时间内的轨道图案并重复轨道图案多次以形成重复的轨道图案。 通过添加一个或多个中间轨道来维持跟踪图案和重复轨迹图案两者的光掩模指定设计规则和轨迹图案设计规则的一致性。 可以通过使用一个或多个中间轨道，从轨道图案添加或移除轨道，或者由与不同宽度相关联的另一轨道替换轨道。 该方法可以验证一段时间，并在有效期内替换无效期。 在识别用于构成重复轨道图案的轨道图案中的轨道期间，该方法还向前预测预定数量的轨道或预测一个或多个轨道达预定距离。

公开(公告)号：US08806405B2

公开(公告)日：2014-08-12

申请号：US13665760

申请日：2012-10-31

Applicant: Cadence Design Systems, Inc.

Inventor： Regis Colwell ,  Arnold Ginetti ,  Khalid ElGalaind ,  Thomas Jordan ,  Jose A. Martinez ,  Jeffrey Markham ,  Steven Riley ,  Chung-Do Yang

IPC: G06F17/50

CPC classification number: G06F17/5077

Abstract: A method is provided to produce a constraint information for use to implement a routing process used to generate routing signal lines in an integrated circuit design comprising: producing a net topology pattern structure that corresponds to a logical net that is associated with at least two instance item structures of at least one functional design, wherein the net topology pattern structure is associated with the at least two instance item structures and includes multiple constituent structures that indicate at least one constraint upon physical implementation of the logical net structure.

Abstract translation: 提供了一种用于产生用于实现用于在集成电路设计中生成路由信号线的路由过程的约束信息的方法，包括：产生对应于与至少两个实例项目相关联的逻辑网络的网络拓扑模式结构 至少一个功能设计的结构，其中所述网络拓扑模式结构与所述至少两个实例项目结构相关联，并且包括指示所述逻辑网络结构的物理实现的至少一个约束的多个组成结构。

公开(公告)号：US20140123094A1

公开(公告)日：2014-05-01

申请号：US13665760

申请日：2012-10-31

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Regis Colwell ,  Arnold Ginetti ,  Khalid ElGalaind ,  Thomas Jordan ,  Jose A. Martinez ,  Jeffrey Markham ,  Steven Riley ,  Chung-Do Yang

IPC: G06F17/50

CPC classification number: G06F17/5077

Abstract: A method is provided to produce a constraint information for use to implement a routing process used to generate routing signal lines in an integrated circuit design comprising: producing a net topology pattern structure that corresponds to a logical net that is associated with at least two instance item structures of at least one functional design, wherein the net topology pattern structure is associated with the at least two instance item structures and includes multiple constituent structures that indicate at least one constraint upon physical implementation of the logical net structure.

Abstract translation: 提供了一种用于产生用于实现用于在集成电路设计中生成路由信号线的路由过程的约束信息的方法，包括：产生对应于与至少两个实例项目相关联的逻辑网络的网络拓扑模式结构 至少一个功能设计的结构，其中所述网络拓扑模式结构与所述至少两个实例项目结构相关联，并且包括指示所述逻辑网络结构的物理实现的至少一个约束的多个组成结构。