Some embodiments of the present disclosure relate to an integrated circuit (IC) arranged on a semiconductor substrate, which includes a flash region, a capacitor region, and a logic region. An upper substrate surface of the capacitor region is recessed relative to respective upper substrate surfaces of the flash and logic regions, respectively. A capacitor, which includes a polysilicon bottom electrode, a conductive top electrode arranged over the polysilicon bottom electrode, and a capacitor dielectric separating the bottom and top electrodes; is disposed over the recessed upper substrate surface of the capacitor region. A flash memory cell is disposed over the upper substrate surface of the flash region. The flash memory cell includes a select gate having a planarized upper surface that is co-planar with a planarized upper surface of the top electrode of the capacitor.