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Invention Grant
US09572261B2 Conductive through-polymer vias for capacitative structures integrated with packaged semiconductor chips 有权
用于与封装的半导体芯片集成的电容结构的导电聚合物通孔

Conductive through-polymer vias for capacitative structures integrated with packaged semiconductor chips
Abstract:
An electronic system comprising an electronic body (301) with terminal pads (310) and at least one capacitor embedded in the electronic body. The capacitor including an insulating and adhesive first polymeric film (302) covering the body surface except the terminal pads; a sheet (320) of high-density capacitive elements, the first capacitor terminal being a metal foil (321) attached to film (302), the second terminal a conductive polymeric compound (324), and the insulator a dielectric skin (323). Sheet (320) has sets of via holes: the first set holes reaching metal foil 321), the second set holes reaching the terminals (310), and the third set holes reaching the conductive polymeric compound (324). An insulating second polymeric film (303) lining the sidewalls of the holes and planarizing the sheet surface; and metal (432) filling the via holes between the polymeric sidewalls and forming conductive traces and attachment pads on the system surface.
Abstract(Chinese):

一种电子系统，包括具有端子焊盘（310）的电子体（301）和嵌入电子体中的至少一个电容器。 所述电容器包括绝缘和粘合的第一聚合物膜（302），所述绝缘和粘合的第一聚合物膜（302）覆盖除了所述端子焊盘之外 高密度电容元件的片材（320），所述第一电容器端子是附着到膜（302）上的金属箔（321），所述第二端子是导电聚合物（324），所述绝缘体是介电性皮层（323） 。 片（320）具有一组通孔：第一组孔到达金属箔321），第二组孔到达端子（310），第三组孔到达导电聚合物（324）。 绝缘的第二聚合物膜（303），其衬在所述孔的侧壁上并平坦化所述片材表面; 和填充聚合物侧壁之间的通孔的金属（432），并在系统表面上形成导电迹线和附着垫。

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