Invention Grant
- Patent Title: Hardware prefetcher for indirect access patterns
- Patent Title (中): 用于间接访问模式的硬件预取器
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Application No.: US14582348Application Date: 2014-12-24
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Publication No.: US09582422B2Publication Date: 2017-02-28
- Inventor: Xiangyao Yu , Christopher J. Hughes , Nadathur Rajagopalan Satish
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: US CA Santa Clara
- Agency: Sheridan Ross, PC
- Agent Jason H. Vick
- Main IPC: G06F12/00
- IPC: G06F12/00 ; G06F12/08 ; G06F9/30 ; G06F9/345

Abstract:
Two techniques address bottlenecking in processors. The first is indirect prefetching. The technique can be especially useful for graph analytics and sparse matrix applications. For graph analytics and sparse matrix applications, the addresses of most random memory accesses come from an index array B which is sequentially scanned by an application. The random accesses are actually indirect accesses in the form A[B[i]]. A hardware component is introduced to detect this pattern. The hardware can then read B a certain distance ahead, and prefetch the corresponding element in A. For example, if the “prefetch distance” is k, when B[i] is accessed, the hardware reads B[i+k], and then A[B[i+k]. For partial cacheline accessing, the indirect accesses are usually accessing random memory locations and only accessing a small portion of a cacheline. Instead of loading the whole cacheline into L1 cache, the second technique only loads a part of the cacheline.
Public/Granted literature
- US20160188476A1 HARDWARE PREFETCHER FOR INDIRECT ACCESS PATTERNS Public/Granted day:2016-06-30
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