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公开(公告)号：US20240354259A1
公开(公告)日：2024-10-24
申请号：US18732865
申请日：2024-06-04
IPC分类号： G06F12/1045 , G06F7/24 , G06F7/487 , G06F7/499 , G06F7/53 , G06F7/57 , G06F9/30 , G06F9/32 , G06F9/345 , G06F9/38 , G06F9/48 , G06F11/00 , G06F11/10 , G06F12/0862 , G06F12/0875 , G06F12/0897 , G06F12/1009 , G06F15/78 , G06F17/16 , H03H17/06
CPC分类号： G06F12/1045 , G06F7/24 , G06F7/487 , G06F7/4876 , G06F7/49915 , G06F7/53 , G06F7/57 , G06F9/3001 , G06F9/30014 , G06F9/30021 , G06F9/30032 , G06F9/30036 , G06F9/30065 , G06F9/30072 , G06F9/30098 , G06F9/30112 , G06F9/30145 , G06F9/30149 , G06F9/3016 , G06F9/32 , G06F9/345 , G06F9/3802 , G06F9/3818 , G06F9/383 , G06F9/3836 , G06F9/3851 , G06F9/3856 , G06F9/3867 , G06F9/3887 , G06F9/48 , G06F11/00 , G06F11/1048 , G06F12/0862 , G06F12/0875 , G06F12/0897 , G06F12/1009 , G06F17/16 , H03H17/0664 , G06F9/30018 , G06F9/325 , G06F9/381 , G06F9/3822 , G06F11/10 , G06F15/7807 , G06F15/781 , G06F2212/452 , G06F2212/60 , G06F2212/602 , G06F2212/68
摘要： A method is provided that includes performing, by a processor in response to a vector matrix multiply instruction, multiplying an m×n matrix (A matrix) and a n×p matrix (B matrix) to generate elements of an m×p matrix (R matrix), and storing the elements of the R matrix in a storage location specified by the vector matrix multiply instruction.
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公开(公告)号：US12106109B2
公开(公告)日：2024-10-01
申请号：US17620527
申请日：2021-04-28
发明人： Xuyan Ma , Jianhua Wu , Shaoli Liu , Xiangxuan Ge , Hanbo Liu , Lei Zhang
CPC分类号： G06F9/355 , G06F9/30043 , G06F9/30047 , G06F9/345
摘要： The present disclosure relates to a data processing apparatus and related products. The data processing apparatus includes a decoding unit, a discrete-address determining unit, a continuous-data caching unit, a data read/write unit, and a storage unit. Through the data processing apparatus, the processing instruction may be decoded and executed. Discrete data may be transferred to a continuous data address, or continuous data may be stored to multiple discrete data addresses. As such, a vector computation of discrete data and vector data restoration after the vector computation may be implemented, which may simplify a processing process, thereby reducing data overhead.
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公开(公告)号：US20240311313A1
公开(公告)日：2024-09-19
申请号：US18660120
申请日：2024-05-09
IPC分类号： G06F12/1045 , G06F7/24 , G06F7/487 , G06F7/499 , G06F7/53 , G06F7/57 , G06F9/30 , G06F9/32 , G06F9/345 , G06F9/38 , G06F9/48 , G06F11/00 , G06F11/10 , G06F12/0862 , G06F12/0875 , G06F12/0897 , G06F12/1009 , G06F15/78 , G06F17/16 , H03H17/06
CPC分类号： G06F12/1045 , G06F7/24 , G06F7/487 , G06F7/4876 , G06F7/49915 , G06F7/53 , G06F7/57 , G06F9/3001 , G06F9/30014 , G06F9/30021 , G06F9/30032 , G06F9/30036 , G06F9/30065 , G06F9/30072 , G06F9/30098 , G06F9/30112 , G06F9/30145 , G06F9/30149 , G06F9/3016 , G06F9/32 , G06F9/345 , G06F9/3802 , G06F9/3818 , G06F9/383 , G06F9/3836 , G06F9/3851 , G06F9/3856 , G06F9/3867 , G06F9/3887 , G06F9/48 , G06F11/00 , G06F11/1048 , G06F12/0862 , G06F12/0875 , G06F12/0897 , G06F12/1009 , G06F17/16 , H03H17/0664 , G06F9/30018 , G06F9/325 , G06F9/381 , G06F9/3822 , G06F11/10 , G06F15/7807 , G06F15/781 , G06F2212/452 , G06F2212/60 , G06F2212/602 , G06F2212/68
摘要： Various configurations of processors are provided. In a configuration, the processor comprises first and second multiplication units. The first multiplication unit includes first multiply circuitry including a first set of outputs; and first multiplexing logic coupled to the first set of outputs and configured to generate a first partial sum and a first partial carry. The second multiplication unit includes second multiply circuitry including a second set of outputs; and second multiplexing logic coupled to the second set of outputs and configured to generate a second partial sum and a first partial carry.
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公开(公告)号：US20240296050A1
公开(公告)日：2024-09-05
申请号：US18655454
申请日：2024-05-06
IPC分类号： G06F9/30 , G06F5/06 , G06F9/32 , G06F9/345 , G06F9/38 , G06F11/00 , G06F11/10 , G06F12/0875 , G06F12/0897
CPC分类号： G06F9/3016 , G06F9/30014 , G06F9/30036 , G06F9/30098 , G06F9/30112 , G06F9/30145 , G06F9/32 , G06F9/345 , G06F9/3802 , G06F9/383 , G06F9/3867 , G06F11/00 , G06F11/1048 , G06F12/0875 , G06F12/0897 , G06F5/06 , G06F9/30043 , G06F9/3822 , G06F11/10 , G06F2205/067 , G06F2212/452 , G06F2212/60
摘要： A stream of data is accessed from a memory system by an autonomous memory access engine, converted on the fly by the memory access engine, and then presented to a processor for data processing. A portion of a lookup table (LUT) containing converted data elements is preloaded into a lookaside buffer associated with the memory access engine. As the stream of data elements is fetched from the memory system each data element in the stream of data elements is replaced with a respective converted data element obtained from the LUT in the lookaside buffer according to a content of each data element to thereby form a stream of converted data elements. The stream of converted data elements is then propagated from the memory access engine to a data processor.
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公开(公告)号：US12045172B2
公开(公告)日：2024-07-23
申请号：US17987020
申请日：2022-11-15
IPC分类号： G06F7/487 , G06F7/24 , G06F7/499 , G06F7/53 , G06F7/57 , G06F9/30 , G06F9/32 , G06F9/345 , G06F9/38 , G06F9/48 , G06F11/00 , G06F11/10 , G06F12/0862 , G06F12/0875 , G06F12/0897 , G06F12/1009 , G06F12/1045 , G06F17/16 , H03H17/06
CPC分类号： G06F12/1045 , G06F7/24 , G06F7/487 , G06F7/4876 , G06F7/49915 , G06F7/53 , G06F7/57 , G06F9/3001 , G06F9/30014 , G06F9/30021 , G06F9/30032 , G06F9/30036 , G06F9/30065 , G06F9/30098 , G06F9/30112 , G06F9/30145 , G06F9/30149 , G06F9/3016 , G06F9/32 , G06F9/345 , G06F9/3802 , G06F9/3818 , G06F9/383 , G06F9/3836 , G06F9/3851 , G06F9/3867 , G06F9/48 , G06F11/00 , G06F11/1048 , G06F12/0862 , G06F12/0875 , G06F12/0897 , G06F12/1009 , G06F17/16 , H03H17/0664 , G06F9/3822 , G06F11/10 , G06F2212/452 , G06F2212/60 , G06F2212/602 , G06F2212/68
摘要： A method is provided that includes performing, by a processor in response to a floating point multiply instruction, multiplication of floating point numbers, wherein determination of values of implied bits of leading bit encoded mantissas of the floating point numbers is performed in parallel with multiplication of the encoded mantissas, and storing, by the processor, a result of the floating point multiply instruction in a storage location indicated by the floating point multiply instruction.
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公开(公告)号：US12032490B2
公开(公告)日：2024-07-09
申请号：US18073313
申请日：2022-12-01
IPC分类号： G06F12/10 , G06F7/24 , G06F7/487 , G06F7/499 , G06F7/53 , G06F7/57 , G06F9/30 , G06F9/32 , G06F9/345 , G06F9/38 , G06F9/48 , G06F11/00 , G06F11/10 , G06F12/0862 , G06F12/0875 , G06F12/0897 , G06F12/1009 , G06F12/1045 , G06F17/16 , H03H17/06 , G06F15/78
CPC分类号： G06F12/1045 , G06F7/24 , G06F7/487 , G06F7/4876 , G06F7/49915 , G06F7/53 , G06F7/57 , G06F9/3001 , G06F9/30014 , G06F9/30021 , G06F9/30032 , G06F9/30036 , G06F9/30065 , G06F9/30072 , G06F9/30098 , G06F9/30112 , G06F9/30145 , G06F9/30149 , G06F9/3016 , G06F9/32 , G06F9/345 , G06F9/3802 , G06F9/3818 , G06F9/383 , G06F9/3836 , G06F9/3851 , G06F9/3856 , G06F9/3867 , G06F9/3887 , G06F9/48 , G06F11/00 , G06F11/1048 , G06F12/0862 , G06F12/0875 , G06F12/0897 , G06F12/1009 , G06F17/16 , H03H17/0664 , G06F9/30018 , G06F9/325 , G06F9/381 , G06F9/3822 , G06F11/10 , G06F15/7807 , G06F15/781 , G06F2212/452 , G06F2212/60 , G06F2212/602 , G06F2212/68
摘要： A method for sorting of a vector in a processor is provided that includes performing, by the processor in response to a vector sort instruction, sorting of values stored in lanes of the vector to generate a sorted vector, wherein the values are sorted in an order indicated by the vector sort instruction, and storing the sorted vector in a storage location.
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公开(公告)号：US20240220258A1
公开(公告)日：2024-07-04
申请号：US18607703
申请日：2024-03-18
发明人： Joseph ZBICIAK
IPC分类号： G06F9/30 , G06F9/345 , G06F9/38 , G06F12/0875
CPC分类号： G06F9/30149 , G06F9/30036 , G06F9/30047 , G06F9/30065 , G06F9/3016 , G06F9/345 , G06F9/3824 , G06F9/383 , G06F12/0875 , G06F2212/452
摘要： A streaming engine employed in a digital signal processor specifies a fixed read only data stream. Once fetched the data stream is stored in two head registers for presentation to functional units in the fixed order. Data use by the functional unit is preferably controlled using the input operand fields of the corresponding instruction. A first read only operand coding supplies data from the first head register. A first read/advance operand coding supplies data from the first head register and also advances the stream to the next sequential data elements. Corresponding second read only operand coding and second read/advance operand coding operate similarly with the second head register. A third read only operand coding supplies double width data from both head registers.
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公开(公告)号：US20240202123A1
公开(公告)日：2024-06-20
申请号：US18594091
申请日：2024-03-04
发明人： Joseph Zbiciak
IPC分类号： G06F12/0815 , G06F9/30 , G06F9/32 , G06F9/345 , G06F9/38 , G06F12/0862 , G06F12/0875 , G06F12/0897 , G06F15/80
CPC分类号： G06F12/0815 , G06F9/3001 , G06F9/30036 , G06F9/30047 , G06F9/30072 , G06F9/3012 , G06F9/3013 , G06F9/30145 , G06F9/345 , G06F9/3822 , G06F9/383 , G06F9/3853 , G06F9/3887 , G06F12/0862 , G06F12/0875 , G06F12/0897 , G06F9/30065 , G06F9/325 , G06F15/8007 , G06F2212/452 , G06F2212/454 , G06F2212/6026 , G06F2212/621
摘要： A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements for the nested loops. A steam head register stores data elements next to be supplied to functional units for use as operands. A stream template specifies loop count and loop dimension for each nested loop. A format definition field in the stream template specifies the number of loops and the stream template bits devoted to the loop counts and loop dimensions. This permits the same bits of the stream template to be interpreted differently enabling trade off between the number of loops supported and the size of the loop counts and loop dimensions.
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公开(公告)号：US11977891B2
公开(公告)日：2024-05-07
申请号：US15012674
申请日：2016-02-01
发明人： Douglas C. Burger , Aaron L. Smith
IPC分类号： G06F9/30 , G06F9/26 , G06F9/32 , G06F9/345 , G06F9/35 , G06F9/38 , G06F9/46 , G06F9/52 , G06F11/36 , G06F12/0806 , G06F12/0862 , G06F12/1009 , G06F13/42 , G06F15/78 , G06F15/80 , G06F9/355 , G06F12/0811 , G06F12/0875
CPC分类号： G06F9/3016 , G06F9/268 , G06F9/30007 , G06F9/30021 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30047 , G06F9/3005 , G06F9/30058 , G06F9/30072 , G06F9/30076 , G06F9/30087 , G06F9/3009 , G06F9/30098 , G06F9/30101 , G06F9/30105 , G06F9/30138 , G06F9/30145 , G06F9/30167 , G06F9/30189 , G06F9/32 , G06F9/345 , G06F9/35 , G06F9/3802 , G06F9/3804 , G06F9/3822 , G06F9/3824 , G06F9/3828 , G06F9/383 , G06F9/3836 , G06F9/3838 , G06F9/3842 , G06F9/3848 , G06F9/3851 , G06F9/3853 , G06F9/3856 , G06F9/38585 , G06F9/3867 , G06F9/3891 , G06F9/466 , G06F9/528 , G06F11/36 , G06F11/3648 , G06F11/3656 , G06F12/0806 , G06F12/0862 , G06F12/1009 , G06F13/4221 , G06F15/7867 , G06F15/80 , G06F15/8007 , G06F9/3013 , G06F9/321 , G06F9/355 , G06F9/3557 , G06F12/0811 , G06F12/0875 , G06F2212/452 , G06F2212/602 , G06F2212/604 , G06F2212/62 , Y02D10/00
摘要： Apparatus and methods are disclosed for controlling execution of memory access instructions in a block-based processor architecture using a hardware structure that generates a relative ordering of memory access instruction in an instruction block. In one example of the disclosed technology, a method of executing an instruction block having a plurality of memory load and/or memory store instructions includes decoding an instruction block encoding a plurality of memory access instructions and generating data indicating a relative order for executing the memory access instructions in the instruction block and scheduling operation of a portion of the instruction block based at least in part on the relative order data. In some examples, a store vector data register can store the generated relative ordering data for use in subsequent instances of the instruction block.
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公开(公告)号：US11934833B2
公开(公告)日：2024-03-19
申请号：US17557712
申请日：2021-12-21
发明人： Joseph Zbiciak
IPC分类号： G06F9/30 , G06F9/345 , G06F9/38 , G06F12/0875
CPC分类号： G06F9/30149 , G06F9/30036 , G06F9/30047 , G06F9/30065 , G06F9/3016 , G06F9/345 , G06F9/3824 , G06F9/383 , G06F12/0875 , G06F2212/452
摘要： A streaming engine employed in a digital signal processor specifies a fixed read only data stream. Once fetched the data stream is stored in two head registers for presentation to functional units in the fixed order. Data use by the functional unit is preferably controlled using the input operand fields of the corresponding instruction. A first read only operand coding supplies data from the first head register. A first read/advance operand coding supplies data from the first head register and also advances the stream to the next sequential data elements. Corresponding second read only operand coding and second read/advance operand coding operate similarly with the second head register. A third read only operand coding supplies double width data from both head registers.
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