Invention Grant
US09582432B2 Instruction and logic for support of code modification in translation lookaside buffers
有权
用于支持翻译后备缓冲区中的代码修改的指令和逻辑
- Patent Title: Instruction and logic for support of code modification in translation lookaside buffers
- Patent Title (中): 用于支持翻译后备缓冲区中的代码修改的指令和逻辑
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Application No.: US15178008Application Date: 2016-06-09
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Publication No.: US09582432B2Publication Date: 2017-02-28
- Inventor: Jaroslaw Topp , Niranjan L. Cooray , Fernando Latorre
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Baker Botts L.L.P.
- Main IPC: G06F12/00
- IPC: G06F12/00 ; G06F13/00 ; G06F12/10 ; G06F9/30
Abstract:
A processor includes a core with logic to execute a translated instruction. The translated instruction is translated from an instruction stored in a memory location. The processor further includes a translation lookaside buffer including logic to store translation indicators from a physical map. Each translation indicator indicates whether a corresponding memory location includes translated code to be protected. The processor further includes a translation indicator agent including logic to determine whether the buffer indicates whether the memory location has been modified subsequent to translation of the instruction.
Public/Granted literature
- US20160292081A1 Instruction and Logic for Support of Code Modification In Translation Lookaside Buffers Public/Granted day:2016-10-06
Information query
