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US09582464B2 Systems, apparatuses, and methods for performing a double blocked sum of absolute differences 有权
用于执行绝对差异的双重阻塞和的系统，装置和方法

Systems, apparatuses, and methods for performing a double blocked sum of absolute differences
摘要：
Embodiments of systems, apparatuses, and methods for performing in a computer processor vector double block packed sum of absolute differences (SAD) in response to a single vector double block packed sum of absolute differences instruction that includes a destination vector register operand, first and second source operands, an immediate, and an opcode are described.
摘要（中）：

用于在计算机处理器中执行的系统，装置和方法的实施例响应于包括目的地向量寄存器操作数的绝对差指令的单向量双块压缩和，绝对差（SAD）的双块压缩和，第一和第二 描述源操作数，立即数和操作码。

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