A method for design template pattern optimization, comprises receiving a design for a fin field effect transistor (FinFET) device, wherein the design includes a configuration of fins, creating a design template pattern for the design for use in connection with directed self-assembly (DSA) patterning using graphoepitaxy, and optimizing the design template pattern to minimize pattern density gradients, wherein the design template pattern includes a plurality of guiding lines for guiding a block-copolymer deposited during the DSA patterning and the optimizing comprises altering the guiding lines.