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公开(公告)号：US10949601B2
公开(公告)日：2021-03-16
申请号：US16729706
申请日：2019-12-30
IPC分类号： G06F30/398 , G06F30/39 , H01L29/66 , G06F119/18
摘要： A method for reducing chemo-epitaxy directed-self assembly (DSA) defects of a layout of a guiding pattern, the method comprising expanding a shape of the guiding pattern by a predetermined distance in both lateral directions to form a fin keep mask, where the fin keep mask comprises a stand-alone mask.
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2.发明申请NEUTRAL HARD MASK AND ITS APPLICATION TO GRAPHOEPITAXY-BASED DIRECTED SELF-ASSEMBLY (DSA) PATTERNING 有权中性硬帘及其应用于基于花岗质的指导自组装（DSA）图案公开(公告)号：US20170025274A1
公开(公告)日：2017-01-26
申请号：US14806921
申请日：2015-07-23
IPC分类号： H01L21/033 , H01L21/027
CPC分类号： H01L21/0337 , B81C1/00396 , G03F7/0002 , G03F7/094
摘要： A material stack is formed on the surface of a semiconductor substrate. The top layer of the material stack comprises at least an organic planarization layer. A neutral hard mask layer is formed on the top of the organic planarization layer. The neutral hard mask layer is neutral to the block copolymers used for direct self-assembly. A plurality of template etch stacks are then formed on top of the neutral hard mask layer. After formation of the template etch stacks, neutrality recovery is performed on the neutral hard mask layer and the top portions of the template etch stacks, the vertical sidewalls of the template etch stacks being substantially unaffected by the neutrality recovery. A template for DSA is thus obtained.
摘要翻译： 材料堆叠形成在半导体衬底的表面上。 材料堆叠的顶层至少包括有机平坦化层。 在有机平坦化层的顶部形成中性硬掩模层。 中性硬掩模层对于用于直接自组装的嵌段共聚物是中性的。 然后在中性硬掩模层的顶部上形成多个模板蚀刻堆叠。 在形成模板蚀刻堆叠之后，在中性硬掩模层和模板蚀刻堆叠的顶部进行中性恢复，模板蚀刻堆叠的垂直侧壁基本上不受中性恢复的影响。 因此获得DSA的模板。
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3.发明申请METHOD AND SYSTEM FOR TEMPLATE PATTERN OPTIMIZATION FOR DSA PATTERNING USING GRAPHOEPITAXY 有权使用纹理特征的DSA图案模板优化的方法和系统公开(公告)号：US20160350465A1
公开(公告)日：2016-12-01
申请号：US14723570
申请日：2015-05-28
发明人： Michael A. Guillorn , Kafai Lai , Melih Ozlem , Hsinyu Tsai
IPC分类号： G06F17/50 , H01L27/088
CPC分类号： G06F17/5072 , G03F7/0002 , G06F17/5068 , G06F2217/12 , H01L27/0886 , Y02P90/265
摘要： A method for design template pattern optimization, comprises receiving a design for a fin field effect transistor (FinFET) device, wherein the design includes a configuration of fins, creating a design template pattern for the design for use in connection with directed self-assembly (DSA) patterning using graphoepitaxy, and optimizing the design template pattern to minimize pattern density gradients, wherein the design template pattern includes a plurality of guiding lines for guiding a block-copolymer deposited during the DSA patterning and the optimizing comprises altering the guiding lines.
摘要翻译： 一种用于设计模板图案优化的方法，包括接收鳍状场效应晶体管（FinFET）器件的设计，其中所述设计包括翅片的构造，为所述设计创建用于与定向自组装结合使用的设计模板图案（ DSA），并且优化设计模板图案以最小化图案密度梯度，其中设计模板图案包括用于引导在DSA图案化期间沉积的嵌段共聚物的多条引导线，并且优化包括改变引导线。
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公开(公告)号：US09306164B1
公开(公告)日：2016-04-05
申请号：US14609709
申请日：2015-01-30
CPC分类号： H01L21/76877 , H01L21/0337 , H01L21/31144 , H01L21/76816 , H01L21/7684 , H01L21/76864 , H01L23/528 , H01L45/06 , H01L45/1226 , H01L45/1253 , H01L45/16
摘要： Structures including alternating first U-shaped electrodes and second U-shaped electrodes and contact pads interconnecting the first and the second U-shaped electrodes are provided. Each of the first U-shaped electrodes includes substantially parallel straight portions connected by a bent portion located on one end of a substrate. Each of the second U-shaped electrodes includes substantially parallel straight portions connected by a bent portion located on an opposite end of the substrate. Every adjacent straight portions of neighboring first and second U-shaped electrodes constitute an electrode pair having a sub-lithographic pitch. Each of the contact pads overlaps and contacts the bent portion of one of the first and the U-shaped electrodes.
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公开(公告)号：US20150233900A1
公开(公告)日：2015-08-20
申请号：US14699329
申请日：2015-04-29
发明人： Ali Afzali-Ardakani , Shu-jen Han , Amal Kasry , Ahmed Maarouf , Glenn J. Martyna , Razvan Nistor , Hsinyu Tsai
IPC分类号： G01N33/531 , H01L21/30
CPC分类号： G01N33/531 , B82Y30/00 , B82Y40/00 , C01B32/194 , G01N33/5308 , G01N33/54373 , G01N33/54393 , G01N33/551 , G01N2400/00 , H01L21/30
摘要： A graphene nanomesh based charge sensor and method for producing a graphene nanomesh based charge sensor. The method includes generating multiple holes in graphene to create a graphene nanomesh with a patterned array of multiple holes; passivating an edge of each of the multiple holes of the graphene nanomesh to allow for functionalization of the graphene nanomesh; and functionalizing the passivated edge of each of the multiple holes of the graphene nanomesh with a chemical compound that facilitates chemical binding of a receptor of a target molecule to the edge of one or more of the multiple holes, wherein the receptor is a molecule that chemically binds to the target molecule, irrespective of the size of the target molecule.
摘要翻译： 一种基于石墨烯纳米薄膜的电荷传感器和用于生产基于石墨烯纳米薄膜的电荷传感器的方法。 该方法包括在石墨烯中产生多个孔以产生具有多个孔的图案化阵列的石墨烯纳米粒子; 钝化石墨烯纳米颗粒的多个孔中的每一个的边缘以允许石墨烯纳米颗粒的官能化; 并且利用促进目标分子的受体与多个孔中的一个或多个的边缘的化学结合的化学化合物使石墨烯纳米粒子的每个多孔的钝化边缘功能化，其中受体是化学上分解的分子 与目标分子结合，不考虑靶分子的大小。
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6.发明授权公开(公告)号：US09057960B2
公开(公告)日：2015-06-16
申请号：US13831570
申请日：2013-03-14
发明人： Luisa D. Bozano , Dario L. Goldfarb , Linda K. Sundberg , Hoa D. Truong , Hsinyu Tsai , Gregory M. Wallraff
摘要： A process and composition for negative tone development comprises providing a photoresist film that generates acidic sites. Irradiating the photoresist film patternwise provides an irradiated film having exposed and unexposed regions where the exposed regions comprise imaged sites. Baking the irradiated film at elevated temperatures produces a baked-irradiated film comprising the imaged sites which after irradiating, baking, or both irradiating and baking comprise acidic imaged sites. Treating the baked-irradiated film with a liquid, gaseous or vaporous weakly basic compound converts the acidic imaged sites to a base treated film having chemically modified acidic imaged sites. Applying a solvent developer substantially dissolves regions of the film that have not been exposed to the radiant energy, where the solvent developer comprises a substantial non-solvent for the chemically modified acidic imaged sites. One-step simultaneous base treatment and solvent development employs a composition comprising a mix of the basic compound and solvent developer.
摘要翻译： 用于负色调发展的方法和组合物包括提供产生酸性位点的光致抗蚀剂膜。 以图形方式照射光致抗蚀剂膜提供具有暴露区域和未曝光区域的照射膜，其中曝光区域包括成像位置。 在升高的温度下烘烤照射的膜产生包含成像部位的焙烤辐射膜，其在照射，烘烤或照射和烘烤之后均包含酸性成像部位。 用液体，气态或气态的弱碱性化合物处理烘烤过的薄膜将酸性成像部位转化为具有化学改性的酸性成像部位的碱处理膜。 施加溶剂显影剂基本上溶解未暴露于辐射能的膜的区域，其中溶剂显影剂包含用于化学改性的酸性成像位点的基本非溶剂。 一步同步碱处理和溶剂开发采用包含碱性化合物和溶剂显影剂混合物的组合物。
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7.发明授权公开(公告)号：US11514326B2
公开(公告)日：2022-11-29
申请号：US16905241
申请日：2020-06-18
发明人： Hsinyu Tsai , Sanjay Kariyappa
摘要： Drift regularization is provided to counteract variation in drift coefficients in analog neural networks. In various embodiments, a method of training an artificial neural network is illustrated. A plurality of weights is randomly initialized. Each of the plurality of weights corresponds to a synapse of an artificial neural network. At least one array of inputs is inputted to the artificial neural network. At least one array of outputs is determined by the artificial neural network based on the at least one array of inputs and the plurality of weights. The at least one array of outputs is compared to ground truth data to determine a first loss. A second loss is determined by adding a drift regularization to the first loss. The drift regularization is positively correlated to variance of the at least one array of outputs. The plurality of weights is updated based on the second loss by backpropagation.
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公开(公告)号：US20180322238A1
公开(公告)日：2018-11-08
申请号：US16037039
申请日：2018-07-17
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5068 , G06F2217/12 , H01L29/66795
摘要： A method for reducing chemo-epitaxy directed-self assembly (DSA) defects of a layout of a guiding pattern, the method comprising: inserting a first external dummy along an external edge of the guiding pattern in a vertical direction; and inserting a second external dummy at a fixed distance from a second edge of the first external dummy, wherein the second external dummy includes a two-dimensional shape such that at least two edges of the second external dummy are parallel to the second edge of the first external dummy.
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公开(公告)号：US09941121B1
公开(公告)日：2018-04-10
申请号：US15413928
申请日：2017-01-24
IPC分类号： H01L21/311 , H01L21/027 , H01L21/02
CPC分类号： H01L21/0273 , H01L21/02118 , H01L21/02274 , H01L21/0228 , H01L21/31138
摘要： Methods for preparing a patterned directed self-assembly layer generally include providing a substrate having a block copolymer layer including a first phase-separated polymer defining a first pattern in the block copolymer layer and a second phase-separated polymer defining a second pattern in the block copolymer layer. The block polymer layer is exposed to a gas pulsing carbon monoxide polymer. The gas pulsing is configured to provide multiple cycles of an etching plasma and a deposition plasma to selectively remove the second pattern of the second phase-separated polymer while leaving behind the first pattern of the first phase-separated polymer on the substrate.
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公开(公告)号：US09884978B2
公开(公告)日：2018-02-06
申请号：US14754664
申请日：2015-06-29
发明人： Joy Cheng , Michael A. Guillorn , Chi-Chun Liu , Jed W. Pitera , Hsinyu Tsai
IPC分类号： C09D201/00 , G03F7/00 , H01L21/027
CPC分类号： C09D201/00 , G03F7/0002 , H01L21/0271
摘要： The disclosure provides methods for directed self-assembly (DSA) of a block co-polymer (BCP). In one embodiment, a method includes: forming an oxide spacer along each of a first sidewall and a second sidewall of a cavity in a semiconductor substrate; forming a neutral layer between the oxide spacers and along a bottom of the cavity; and removing the oxide spacers to expose the first and second sidewalls and a portion of the bottom of the cavity adjacent the first and second sidewalls.
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