A memory self-testing device for testing a plurality of memory control units includes: a test control unit, coupled to the memory control units, generating a plurality of access request signals and a plurality of sets of data; a channel control unit, coupled to the test control unit and the memory control units, determining a leading feedback signal among a plurality of feedback signals; and a data control unit, coupled to the test control unit and the memory control units, storing the sets of data, and transmitting the sets of data to the memory control units according to a plurality of read/write signals. The feedback signals and the read/write signals are generated by the memory control units in response to the access request signals. The test control units generate the sets of data according to the leading feedback signal.