发明授权
US09590658B1 High-speed low-power LDPC decoder design 有权
高速低功耗LDPC解码器设计

High-speed low-power LDPC decoder design
摘要:
Decoding an LDPC encoded codeword is disclosed. Variable nodes corresponding to a parity check matrix of the LDPC encoded codeword have been divided into a plurality of groups. A selected group of variable nodes from the plurality of groups of variable nodes is updated. Check nodes are updated using a min-sum update. A selected input value provided from a variable node of the selected group of variable nodes and provided to a certain check node of the check nodes is discarded to be not available for use in a future min-sum update.
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