Invention Grant
- Patent Title: Three dimensional memory array architecture
- Patent Title (中): 三维内存阵列架构
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Application No.: US15011816Application Date: 2016-02-01
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Publication No.: US09595667B2Publication Date: 2017-03-14
- Inventor: Federico Pio
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Brooks, Cameron & Huebsch, PLLC
- Main IPC: H01L45/00
- IPC: H01L45/00 ; H01L27/22 ; H01L27/24 ; H01L27/10 ; H01L27/06

Abstract:
Three dimension memory arrays and methods of forming the same are provided. An example three dimension memory array can include a stack comprising a plurality of first conductive lines separated from one another by at least an insulation material, and at least one conductive extension arranged to extend substantially perpendicular to the plurality of first conductive lines, such that the at least one conductive extension intersects a portion of at least one of the plurality of first conductive lines. Storage element material is formed around the at least one conductive extension. Cell select material is formed around the at least one conductive extension.
Public/Granted literature
- US20160149126A1 THREE DIMENSIONAL MEMORY ARRAY ARCHITECTURE Public/Granted day:2016-05-26
Information query
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