A method and an apparatus for generating an internal memory clock are provided. The apparatus includes a pulse generator configured to receive a first clock signal in a first power domain and initiate a second clock signal in a second power domain in response to the first clock signal. The first power domain provides a first voltage for logic operations and the second power domain provides a second voltage for memory operations. The apparatus includes a tracking circuit configured to generate a reset signal based on a voltage level of the first power domain. The reset signal may be configured to reset the pulse generator in the first power domain. The apparatus may further include a latch configured to receive the second clock signal in the second power domain.