公开(公告)号：US11074967B2

公开(公告)日：2021-07-27

申请号：US17039845

申请日：2020-09-30

Applicant: QUALCOMM Incorporated

Inventor： Adithya Bhaskaran ,  Mukund Narasimhan ,  Shiba Narayan Mohanty

IPC: G11C11/419 ,  G11C7/12 ,  G11C5/14 ,  G05F3/26

Abstract: A memory is provided that includes a current mirror that controls the amount of current conducted by a head-switch transistor for a memory power supply rail during a core-power-lowering write assist period.

公开(公告)号：US20200251163A1

公开(公告)日：2020-08-06

申请号：US16269463

申请日：2019-02-06

Applicant: QUALCOMM Incorporated

Inventor： Adithya Bhaskaran ,  Mukund Narasimhan ,  Shiba Narayan Mohanty

IPC: G11C11/419 ,  G05F3/26 ,  G11C5/14 ,  G11C7/12

Abstract: A memory is provided that includes a current mirror that controls the amount of current conducted by a head-switch transistor for a memory power supply rail during a core-power-lowering write assist period.

公开(公告)号：US10446196B1

公开(公告)日：2019-10-15

申请号：US16164108

申请日：2018-10-18

Applicant: QUALCOMM Incorporated

Inventor： Mukund Narasimhan ,  Sharad Kumar Gupta ,  Adithya Bhaskaran ,  Sei Seung Yoon

IPC: G11C5/14 ,  G11C11/417

Abstract: A dual-power-domain SRAM is disclosed in which the dual power domains may be powered up or down in whatever order is desired. For example, a (CX) power domain may be powered up first, followed by a memory (MX) power domain. Conversely, the MX power domain may be powered up prior to the CX domain.

公开(公告)号：US09928889B1

公开(公告)日：2018-03-27

申请号：US15465239

申请日：2017-03-21

Applicant: QUALCOMM Incorporated

Inventor： Mukund Narasimhan ,  Rakesh Kumar Sinha ,  Sharad Kumar Gupta ,  Veerabhadra Rao Boda

IPC: G11C11/419 ,  G11C7/12 ,  G11C7/14 ,  G11C7/22 ,  G11C7/06 ,  G06F1/32

CPC classification number: G11C7/12 ,  G06F1/3275 ,  G11C7/062 ,  G11C7/1075 ,  G11C7/14 ,  G11C7/22 ,  G11C7/222 ,  G11C7/227 ,  G11C8/16 ,  G11C11/419

Abstract: A write precharge period for a pseudo-dual-port memory is initiated by an edge (rising or falling) of a read precharge signal. The same edge type (rising or falling) of a write precharge signal signals the end of the write precharge period.

公开(公告)号：US10854246B1

公开(公告)日：2020-12-01

申请号：US16421365

申请日：2019-05-23

Applicant: QUALCOMM Incorporated

Inventor： Adithya Bhaskaran ,  Mukund Narasimhan ,  Shiba Narayan Mohanty

IPC: G11C7/06 ,  G11C7/10 ,  H03K19/20

Abstract: A read path for a memory is provided that includes an integrated sense mixing and redundancy shift stage coupled between a sense amplifier and a data latch. The data latch is integrated with a level shifter.

公开(公告)号：US09865337B1

公开(公告)日：2018-01-09

申请号：US15466749

申请日：2017-03-22

Applicant: QUALCOMM Incorporated

Inventor： Fahad Ahmed ,  Mukund Narasimhan ,  Raghav Gupta ,  Pradeep Raj ,  Rahul Sahu ,  Po-Hung Chen ,  Chulmin Jung

IPC: G11C5/10 ,  G11C11/419 ,  G11C11/417

CPC classification number: G11C11/419 ,  G11C5/14 ,  G11C7/1096 ,  G11C7/12 ,  G11C11/417

Abstract: A write driver is provided that includes a first write driver inverter that inverts a data signal to drive a gate of a second write driver transistor. The write driver transistor has a terminal coupled to a bit line and another terminal coupled to a boost capacitor. A ground for the first write driver inverter floats during a write assist period to choke off leakage of boost charge from the boost capacitor through the write driver transistor.

公开(公告)号：US11315609B2

公开(公告)日：2022-04-26

申请号：US17039742

申请日：2020-09-30

Applicant: QUALCOMM Incorporated

Inventor： Adithya Bhaskaran ,  Mukund Narasimhan ,  Shiba Narayan Mohanty

IPC: G11C7/00 ,  G11C7/06 ,  G11C7/10 ,  H03K19/20

Abstract: A read path for a memory is provided that includes an integrated sense mixing and redundancy shift stage coupled between a sense amplifier and a data latch. The data latch is integrated with a level shifter.

公开(公告)号：US10832764B2

公开(公告)日：2020-11-10

申请号：US16269463

申请日：2019-02-06

Applicant: QUALCOMM Incorporated

Inventor： Adithya Bhaskaran ,  Mukund Narasimhan ,  Shiba Narayan Mohanty

IPC: G11C11/419 ,  G11C7/12 ,  G11C5/14 ,  G05F3/26

Abstract: A memory is provided that includes a current mirror that controls the amount of current conducted by a head-switch transistor for a memory power supply rail during a core-power-lowering write assist period.

公开(公告)号：US10140224B2

公开(公告)日：2018-11-27

申请号：US15461184

申请日：2017-03-16

Applicant: QUALCOMM Incorporated

Inventor： Mukund Narasimhan ,  Sharad Kumar Gupta ,  Dharaneedharan Shanmugasundaram

IPC: G11C11/00 ,  G06F13/16 ,  G11C7/10 ,  G11C11/418 ,  G11C11/419 ,  G11C7/02 ,  G11C7/12

Abstract: In an aspect of the disclosure, an apparatus is provided. In one aspect, the apparatus is a memory apparatus. The memory apparatus includes a memory. The memory includes first and second bitcell arrays. The memory apparatus also includes a sense amplifier. The sense amplifier is shared by the first and the second bitcell arrays. Additionally, the sense amplifier is configured to amplify data stored in the memory during a read operation. The memory apparatus also includes a write circuit. The write circuit is configured to write data to the memory during a write operation. The memory apparatus also includes a controller. The controller is configured to disable the write circuit during the read operation.

公开(公告)号：US09865316B2

公开(公告)日：2018-01-09

申请号：US15003444

申请日：2016-01-21

Applicant: QUALCOMM Incorporated

Inventor： Sharad Kumar Gupta ,  Mukund Narasimhan ,  Veerabhadra Rao Boda

IPC: G11C7/00 ,  G11C7/22 ,  G11C11/419 ,  G11C11/418 ,  G11C7/12 ,  G11C8/08 ,  G11C8/10 ,  G11C8/18

CPC classification number: G11C7/227 ,  G11C7/12 ,  G11C7/22 ,  G11C8/08 ,  G11C8/10 ,  G11C8/18 ,  G11C11/418 ,  G11C11/419 ,  G11C2207/229

Abstract: A memory is provided in which the word line assertion during a write operation is delayed until the discharge of a dummy bit line is detected.