- 专利标题: Method of operating memory array having divided apart bit lines and partially divided bit line selector switches
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申请号: US15161767申请日: 2016-05-23
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公开(公告)号: US09608043B2公开(公告)日: 2017-03-28
- 发明人: Seiji Shimabukuro , Teruyuki Mine , Hiroyuki Ogawa , Naoki Takeguchi
- 申请人: SanDisk Technologies LLC
- 申请人地址: US TX Plano
- 专利权人: SanDisk Technologies LLC
- 当前专利权人: SanDisk Technologies LLC
- 当前专利权人地址: US TX Plano
- 代理机构: Vierra Magen Marcus LLP
- 主分类号: G11C5/02
- IPC分类号: G11C5/02 ; H01L27/24 ; G11C13/00 ; H01L45/00 ; G11C7/18
摘要:
A non-volatile data storage device comprises pairs of immediately adjacent and isolated-from-one-another local bit lines that are independently driven by respective and vertically oriented bit line selector devices. The isolation between the immediately adjacent and isolated-from-one-another local bit lines also isolates from one another respective memory cells of the non-volatile data storage device such that leakage currents cannot flow from memory cells connected to a first of the immediately adjacent and isolated-from-one-another local bit lines to memory cells connected to the second of the pair of immediately adjacent and isolated-from-one-another local bit lines. A method programming a desire one of the memory cells includes applying boosting voltages to word lines adjacent to the bit line of the desired memory cell while not applying boosting voltages to word lines adjacent to the other bit line of the pair.
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