Invention Grant
- Patent Title: Method and structure to reduce parasitic capacitance in raised source/drain silicon-on-insulator devices
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Application No.: US14639232Application Date: 2015-03-05
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Publication No.: US09608080B2Publication Date: 2017-03-28
- Inventor: Ahmet S. Ozcan , Emmanuel Petitprez
- Applicant: International Business Machines Corporation , STMicroelectronics (Crolles 2) SAS
- Applicant Address: US NY Armonk FR Crolles
- Assignee: International Business Machines Corporation,STMICROELECTRONICS (CROLLES 2) SAS
- Current Assignee: International Business Machines Corporation,STMICROELECTRONICS (CROLLES 2) SAS
- Current Assignee Address: US NY Armonk FR Crolles
- Agency: Hoffman Warnick LLC
- Agent Steven J. Meyers
- Main IPC: H01L29/417
- IPC: H01L29/417 ; H01L29/16 ; H01L29/06 ; H01L29/423 ; H01L29/51 ; H01L29/78 ; H01L29/66

Abstract:
An aspect of the invention is directed to a silicon-on-insulator device including a silicon layer on an insulating layer on a substrate; a raised source and a raised drain on the silicon layer; a gate between the raised source and the raised drain; a first spacer separating the gate from the raised source and substantially covering a first sidewall of the gate; a second spacer separating the gate from the raised drain and substantially covering a second sidewall of the gate; and a low-k layer over the raised source, the raised drain, the gate and each of the first spacer and the second spacer; and a dielectric layer over the low-k layer.
Public/Granted literature
- US20160260811A1 METHOD AND STRUCTURE TO REDUCE PARASITIC CAPACITANCE IN RAISED SOURCE/DRAIN SILICON-ON-INSULATOR DEVICES Public/Granted day:2016-09-08
Information query
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