- 专利标题： Self-aligned metal oxide TFT with reduced number of masks and with reduced power consumption
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申请号： US15080231申请日： 2016-03-24
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公开(公告)号： US09614102B2公开(公告)日： 2017-04-04
- 发明人: Chan-Long Shieh , Gang Yu , Fatt Foong
- 申请人： Chan-Long Shieh , Gang Yu , Fatt Foong
- 申请人地址： US CA Goleta
- 专利权人： CBRITE INC.
- 当前专利权人： CBRITE INC.
- 当前专利权人地址： US CA Goleta
- 代理机构： Parsons & Goltry
- 代理商 Robert A. Parsons; Michael W. Goltry
- 主分类号： H01L29/786
- IPC分类号： H01L29/786 ; H01L27/12 ; H01L29/66 ; H01L21/70 ; H01L21/02
摘要：
A method of fabricating MO TFTs includes positioning opaque gate metal on a transparent substrate to define a gate area. Depositing gate dielectric material overlying the gate metal and a surrounding area, and depositing metal oxide semiconductor material thereon. Depositing etch stop material on the semiconductor material. Positioning photoresist defining an isolation area in the semiconductor material, the etch stop material and the photoresist being selectively removable. Exposing the photoresist from the rear surface of the substrate and removing exposed portions to leave the etch stop material uncovered except for a portion overlying and aligned with the gate metal. Etching uncovered portions of the semiconductor material to isolate the TFT. Using the photoresist, selectively etching the etch stop layer to leave a portion overlying and aligned with the gate metal and defining a channel area in the semiconductor material. Depositing and patterning conductive material to form source and drain areas.
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