Invention Grant
- Patent Title: Process for integrated circuit fabrication including a liner silicide with low contact resistance
-
Application No.: US14942504Application Date: 2015-11-16
-
Publication No.: US09633909B2Publication Date: 2017-04-25
- Inventor: Walter Kleemeier , Qing Liu
- Applicant: STMicroelectronics, Inc.
- Applicant Address: US TX Coppell
- Assignee: STMicroelectronics, Inc.
- Current Assignee: STMicroelectronics, Inc.
- Current Assignee Address: US TX Coppell
- Agency: Gardere Wynne Sewell LLP
- Main IPC: H01L21/38
- IPC: H01L21/38 ; H01L21/22 ; H01L21/8238 ; H01L29/45 ; H01L27/092 ; H01L27/12 ; H01L21/02 ; H01L21/84 ; H01L29/66 ; H01L29/78 ; H01L29/778

Abstract:
An integrated circuit includes a substrate supporting a transistor having a source region and a drain region. A high dopant concentration delta-doped layer is present on the source region and drain region of the transistor. A set of contacts extend through a pre-metal dielectric layer covering the transistor. A silicide region is provided at a bottom of the set of contacts. The silicide region is formed by a salicidation reaction between a metal present at the bottom of the contact and the high dopant concentration delta-doped layer on the source region and drain region of the transistor.
Public/Granted literature
- US20160118305A1 PROCESS FOR INTEGRATED CIRCUIT FABRICATION INCLUDING A LINER SILICIDE WITH LOW CONTACT RESISTANCE Public/Granted day:2016-04-28
Information query
IPC分类: