A memory device includes first and second memory cell arrays, a first controller, and a second controller. The first controller controls the first memory cell array through first word line signals and first bit line signals to execute an operation corresponding to a command signal based on an address signal and a data signal. The second controller includes first and second mode registers. The second controller writes sampled values of the address signal and the command signal to the second memory cell array through access signals to form a log in response to stored values of the first and second mode registers or reads stored values of the second memory cell array as the data signal through the access signals.