Invention Grant
- Patent Title: System and apparatus for clock retiming with catch-up mode and associated methods
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Application No.: US14523599Application Date: 2014-10-24
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Publication No.: US09647824B2Publication Date: 2017-05-09
- Inventor: Kenneth W. Fernald , Imranul Islam
- Applicant: Silicon Laboratories Inc.
- Applicant Address: US TX Austin
- Assignee: Silicon Laboratories Inc.
- Current Assignee: Silicon Laboratories Inc.
- Current Assignee Address: US TX Austin
- Agency: Law Offices of Maximilian R. Peterson
- Main IPC: H04L7/00
- IPC: H04L7/00 ; H04L7/033

Abstract:
An apparatus includes analog or mixed-signal circuitry that operates in response to a first signal, and digital circuitry that operates in response to a second signal. The apparatus further includes a signal retiming circuit. The signal retiming circuit retimes an output signal of a digital signal source to reduce interference between the digital circuitry and the analog or mixed-signal circuitry by retiming edges of the output signal of the digital signal source to fall on cycle boundaries of the first signal.
Public/Granted literature
- US20160119111A1 System and Apparatus for Clock Retiming with Catch-Up Mode and Associated Methods Public/Granted day:2016-04-28
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