Invention Grant
- Patent Title: Hiding page translation miss latency in program memory controller by next page prefetch on crossing page boundary
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Application No.: US14581487Application Date: 2014-12-23
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Publication No.: US09652402B2Publication Date: 2017-05-16
- Inventor: Ramakrishnan Venkatasubramanian , Oluleye Olorode
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent Robert D. Marshall, Jr.; Charles A. Brill; Frank D. Cimino
- Main IPC: G06F12/10
- IPC: G06F12/10 ; G06F12/1027 ; G06F12/1009
Abstract:
This invention hides the page miss translation latency for program fetches. In this invention whenever an access is requested by CPU that crosses a memory page boundary, the L1I cache controller request a next page translation along with the current page. This pipelines requests to the μTLB without waiting for L1I cache controller to begin processing the next page requests. This becomes a deterministic prefetch of the second page translation request. The translation information for the second page is stored locally in L1I cache controller and used when the access crosses the next page boundary.
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