Invention Grant
- Patent Title: Electrical interconnect structure for an embedded semiconductor device package and method of manufacturing thereof
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Application No.: US14464877Application Date: 2014-08-21
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Publication No.: US09653438B2Publication Date: 2017-05-16
- Inventor: Paul Alan McConnelee , Arun Virupaksha Gowda
- Applicant: General Electric Company
- Applicant Address: US NY Schenectady
- Assignee: General Electric Company
- Current Assignee: General Electric Company
- Current Assignee Address: US NY Schenectady
- Agency: Ziolkowski Patent Solutions Group, SC
- Main IPC: H01L29/74
- IPC: H01L29/74 ; H01L31/111 ; H01L23/48 ; H01L23/52 ; H01L29/40 ; H01L21/44 ; H01L21/48 ; H01L21/50 ; H01L21/4763 ; H01L25/16 ; H01L23/538 ; H01L23/00 ; H01L21/768 ; H01L23/522 ; H01L23/528 ; H01L23/532 ; H01L25/00 ; H01L25/10 ; H01L23/498
Abstract:
An electronics package includes a first dielectric substrate having a first plurality of vias formed through a thickness thereof, a metalized contact layer coupled to a top surface of the first dielectric substrate, and a first die positioned within a first die opening formed through the thickness of the first dielectric substrate. Metalized interconnects are formed on a bottom surface of the first dielectric substrate and extend through the first plurality of vias to contact the metalized contact layer. A second dielectric substrate is coupled to the first dielectric substrate and has a second plurality of vias formed through a thickness thereof. Metalized interconnects extend through the second plurality of vias to contact the first plurality of metalized interconnects and contact pads of the first die. A first conductive element electrically couples the first die to the metalized contact layer.
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