A three dimensional semiconductor memory device includes a vertical channel structure extending in a vertical direction on a substrate; interlayer insulating layers surrounding the vertical channel structure and being stacked in the vertical direction on the substrate, gate electrodes surrounding the vertical channel structure and being disposed between the interlayer insulating layers, corners of the gate electrodes adjacent to the vertical channel structure being rounded, and auxiliary gate insulating patterns disposed between the gate electrodes and the vertical channel structure, wherein a side surface of the auxiliary gate insulating pattern is substantially coplanar with a side surface of the interlayer insulating layer in the vertical direction on the substrate.