公开(公告)号：US08962444B2

公开(公告)日：2015-02-24

申请号：US14053913

申请日：2013-10-15

申请人： Samsung Electronics Co., Ltd

发明人： Jung-Hwan Kim ,  Sunggil Kim ,  HongSuk Kim ,  Guk-Hyon Yon ,  Hunhyeong Lim

IPC分类号： H01L21/76 ,  H01L21/762

CPC分类号： H01L21/76224 ,  H01L21/28273 ,  H01L21/32155 ,  H01L21/764 ,  H01L27/11524

摘要： Methods of manufacturing a semiconductor device are provided. The method includes forming a poly-silicon layer doped with first p-type dopants on a substrate, etching the poly-silicon layer and the substrate to form a poly-silicon pattern and a trench, forming device isolation pattern covering a lower sidewall of the poly-silicon pattern in the trench, thermally treating the poly-silicon pattern in a gas including second p-type dopants, forming a dielectric layer and a conductive layer on the thermally treated poly-silicon pattern and the device isolation pattern, etching the conductive layer, the dielectric layer, and the thermally treated poly-silicon pattern to form a control gate, a dielectric pattern, and a floating gate respectively.

摘要翻译： 提供制造半导体器件的方法。 该方法包括在衬底上形成掺杂有第一p型掺杂剂的多晶硅层，蚀刻多晶硅层和衬底以形成多晶硅图案和沟槽，从而形成覆盖层的下侧壁的器件隔离图案 沟槽中的多晶硅图案，在包括第二p型掺杂剂的气体中热处理多晶硅图案，在热处理的多晶硅图案和器件隔离图案上形成电介质层和导电层，蚀刻导电 层，电介质层和热处理的多晶硅图案，以分别形成控制栅极，电介质图案和浮置栅极。

公开(公告)号：US09653565B2

公开(公告)日：2017-05-16

申请号：US14865078

申请日：2015-09-25

申请人： Samsung Electronics Co., Ltd

发明人： Byong-hyun Jang ,  Dongchul Yoo ,  Jaeyoung Ahn ,  Hunhyeong Lim

IPC分类号： H01L29/49 ,  H01L27/11582

CPC分类号： H01L29/495 ,  H01L27/11582

摘要： A three dimensional semiconductor memory device includes a vertical channel structure extending in a vertical direction on a substrate; interlayer insulating layers surrounding the vertical channel structure and being stacked in the vertical direction on the substrate, gate electrodes surrounding the vertical channel structure and being disposed between the interlayer insulating layers, corners of the gate electrodes adjacent to the vertical channel structure being rounded, and auxiliary gate insulating patterns disposed between the gate electrodes and the vertical channel structure, wherein a side surface of the auxiliary gate insulating pattern is substantially coplanar with a side surface of the interlayer insulating layer in the vertical direction on the substrate.

公开(公告)号：US09960182B2

公开(公告)日：2018-05-01

申请号：US15634555

申请日：2017-06-27

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Ji-Hoon Choi ,  SeungHyun Lim ,  Sunggil Kim ,  HongSuk Kim ,  Hunhyeong Lim ,  Hyunjun Sim

IPC分类号： H01L27/115 ,  H01L29/10 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/1157

CPC分类号： H01L27/11582 ,  H01L27/11565 ,  H01L27/1157

摘要： A semiconductor memory device includes a stack including gate electrodes sequentially stacked on a substrate, a vertical insulating structure penetrating the stack vertically with respect to the gate electrodes, a vertical channel portion disposed on an inner side surface of the vertical insulating structure, and a common source region formed in the substrate and spaced apart from the vertical channel portion. A bottom region of the vertical channel portion has a protruding surface in contact with a bottom region of the vertical insulating structure.