Invention Grant
- Patent Title: Two step metallization formation
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Application No.: US14523256Application Date: 2014-10-24
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Publication No.: US09659856B2Publication Date: 2017-05-23
- Inventor: Ya-Lien Lee , Chun-Chieh Lin
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater Matsil, LLP
- Main IPC: H01L23/522
- IPC: H01L23/522 ; H01L21/768 ; H01L23/532 ; H01L23/48 ; H01L21/4763

Abstract:
An integrated circuit structure includes a first conductive line, a dielectric layer over the first conductive line, a diffusion barrier layer in the dielectric layer, and a second conductive line in the dielectric layer. The second conductive line includes a first portion of the diffusion barrier layer. A via is underlying the second conductive line and electrically couples the second conductive line to the first conductive line. The via includes a second portion of the diffusion barrier layer, with the second portion of the diffusion barrier layer having a bottom end higher than a bottom surface of the via.
Public/Granted literature
- US20160118335A1 TWO STEP METALLIZATION FORMATION Public/Granted day:2016-04-28
Information query
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