Invention Grant
- Patent Title: Metal pad offset for multi-layer metal layout
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Application No.: US14809580Application Date: 2015-07-27
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Publication No.: US09659859B2Publication Date: 2017-05-23
- Inventor: I-Chih Chen , Ying-Hao Chen , Chi-Cherng Jeng , Volume Chien , Fu-Tsun Tsai , Kun-Huei Lin
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-chu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee Address: TW Hsin-chu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L23/522
- IPC: H01L23/522 ; H01L23/48 ; G06F17/50 ; H01L23/31 ; H01L23/528 ; H01L21/768 ; H01L23/532 ; H01L23/00
Abstract:
A semiconductor device includes a first layer including a number of first layer metal pads, a second layer formed on top of the first layer, the second layer including a number of second layer metal pads, and vias connecting the first layer metal pads to the second layer metal pads. A surface area overlap between the first layer metal pads and the second layer metal pads is below a defined threshold.
Public/Granted literature
- US20150333007A1 METAL PAD OFFSET FOR MULTI-LAYER METAL LAYOUT Public/Granted day:2015-11-19
Information query
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