Invention Grant
- Patent Title: Semiconductor devices including stair step structures, and related methods
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Application No.: US14877997Application Date: 2015-10-08
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Publication No.: US09659950B2Publication Date: 2017-05-23
- Inventor: Aaron Yip , Qiang Tang , Chang Wan Ha
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: MICRON TECHNOLOGY, INC.
- Current Assignee: MICRON TECHNOLOGY, INC.
- Current Assignee Address: US ID Boise
- Agency: TraskBritt
- Main IPC: H01L27/115
- IPC: H01L27/115 ; H01L27/11556 ; G11C16/06

Abstract:
Semiconductor devices, such as three-dimensional memory devices, include a memory array including a stack of conductive tiers and a stair step structure. The stair step structure is positioned between first and second portions of the memory array and includes contact regions for respective conductive tiers of the stack of conductive tiers. The first portion of the memory array includes a first plurality of select gates extending in a particular direction over the stack. The second portion of the memory array includes a second plurality of select gates also extending in the particular direction over the stack of conductive tiers. Methods of forming and methods of operating such semiconductor devices, including vertical memory devices, are also disclosed.
Public/Granted literature
- US20160027793A1 SEMICONDUCTOR DEVICES INCLUDING STAIR STEP STRUCTURES, AND RELATED METHODS Public/Granted day:2016-01-28
Information query
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