公开(公告)号：US20180191528A1

公开(公告)日：2018-07-05

申请号：US15904660

申请日：2018-02-26

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Qiang Tang ,  Xiaojiang Guo ,  Chang Wan Ha

IPC: H04L25/02 ,  G11C29/02 ,  G06F13/40 ,  G11C29/50 ,  G11C5/04

CPC classification number: H04L25/0278 ,  G06F13/4086 ,  G11C5/04 ,  G11C29/025 ,  G11C29/028 ,  G11C29/50008

Abstract: Methods of operating integrated circuit devices include generating a voltage level at a particular node in response to a first voltage level applied to a termination device and a second voltage level applied to a reference resistance; determining whether a plurality of available resistance values of the termination device satisfy a criterion that each available resistance value is either less than a resistance value of the reference resistance, or each available resistance value is greater than the resistance value of the reference resistance; and, when the plurality of available resistance values of the termination device satisfy the criterion, determining whether a voltage level generated at the particular node for a particular available resistance value of the plurality of available resistance values is between a voltage level of a first reference voltage and a voltage level of a second reference voltage.

公开(公告)号：US09880609B2

公开(公告)日：2018-01-30

申请号：US15226505

申请日：2016-08-02

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Chang Wan Ha ,  Hang Tian ,  Jong Kang

IPC: G06F1/00 ,  H04L12/28 ,  G06F1/32 ,  G11C7/10 ,  G11C7/22 ,  G06F1/12 ,  G06F13/16

CPC classification number: G06F1/324 ,  G06F1/12 ,  G06F1/3237 ,  G06F1/3275 ,  G06F13/1673 ,  G11C7/1015 ,  G11C7/222 ,  Y02B70/12 ,  Y02B70/123 ,  Y02B70/126 ,  Y02D10/128 ,  Y02D10/13 ,  Y02D10/14

Abstract: Apparatus facilitating peak power management are useful in mitigating excessive current levels within a multi-die package. For example, such apparatus may include an array of memory cells, a controller for performing an access operation on the array of memory cells, an input buffer having an input connected to a clock signal line and having an output, a clock generator for generating an internal clock signal, an output buffer having an input connected to receive the internal clock signal and having an output connected to the clock signal line, and a counter for counting pulses of a particular clock signal selected from a group consisting of the internal clock signal from the clock generator and an external clock signal from the output of the input buffer.

公开(公告)号：US09672156B2

公开(公告)日：2017-06-06

申请号：US15083130

申请日：2016-03-28

Applicant: Micron Technology, Inc.

Inventor： Chang Wan Ha

IPC: G11C16/04 ,  G06F12/0875 ,  G11C16/34 ,  G11C8/10 ,  G06F12/0893 ,  G11C16/10 ,  G06F12/02

CPC classification number: G06F12/0875 ,  G06F12/0246 ,  G06F12/0893 ,  G06F2212/2022 ,  G06F2212/3042 ,  G06F2212/452 ,  G06F2212/7203 ,  G11C8/10 ,  G11C16/0425 ,  G11C16/0433 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3454

Abstract: Dynamic data caches (DDCs), decoders and decoding methods that may fit into a smaller width area. The DDCs, decoders and decoding method may be used in flash memory devices. A single column select line may be provided to select a plurality of cached bytes, while a second select line selects a byte of the selected plurality. The column select line may be routed parallel to bit lines carrying data, while the second select line may be routed perpendicular to the bit lines.

公开(公告)号：US09659950B2

公开(公告)日：2017-05-23

申请号：US14877997

申请日：2015-10-08

Applicant: Micron Technology, Inc.

Inventor： Aaron Yip ,  Qiang Tang ,  Chang Wan Ha

IPC: H01L27/115 ,  H01L27/11556 ,  G11C16/06

CPC classification number: H01L27/11556 ,  G11C16/06 ,  H01L27/115 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582

Abstract: Semiconductor devices, such as three-dimensional memory devices, include a memory array including a stack of conductive tiers and a stair step structure. The stair step structure is positioned between first and second portions of the memory array and includes contact regions for respective conductive tiers of the stack of conductive tiers. The first portion of the memory array includes a first plurality of select gates extending in a particular direction over the stack. The second portion of the memory array includes a second plurality of select gates also extending in the particular direction over the stack of conductive tiers. Methods of forming and methods of operating such semiconductor devices, including vertical memory devices, are also disclosed.

公开(公告)号：US20160210236A1

公开(公告)日：2016-07-21

申请号：US15083130

申请日：2016-03-28

Applicant: Micron Technology, Inc.

Inventor： Chang Wan Ha

IPC: G06F12/08

CPC classification number: G06F12/0875 ,  G06F12/0246 ,  G06F12/0893 ,  G06F2212/2022 ,  G06F2212/3042 ,  G06F2212/452 ,  G06F2212/7203 ,  G11C8/10 ,  G11C16/0425 ,  G11C16/0433 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3454

Abstract: Examples described include dynamic data caches (DDCs), decoders and decoding methods that may fit into a smaller width area. The DDCs, decoders and decoding method may be used in flash memory devices. A single column select line may be provided to select a plurality of cached bytes, while a second select line selects a byte of the selected plurality. The column select line may be routed parallel to bit lines carrying data, while the second select line may be routed perpendicular to the bit lines.

Abstract translation: 所描述的示例包括可适应于较小宽度区域的动态数据高速缓存（DDC），解码器和解码方法。 DDC，解码器和解码方法可用于闪存设备。 可以提供单列选择线来选择多个缓存字节，而第二选择线选择所选择的多个字节。 列选择线可以平行于承载数据的位线被路由，而第二选择线可以垂直于位线被路由。

公开(公告)号：US20160027793A1

公开(公告)日：2016-01-28

申请号：US14877997

申请日：2015-10-08

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Aaron Yip ,  Qiang Tang ,  Chang Wan Ha

IPC: H01L27/115 ,  G11C16/06

CPC classification number: H01L27/11556 ,  G11C16/06 ,  H01L27/115 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582

Abstract: Semiconductor devices, such as three-dimensional memory devices, include a memory array including a stack of conductive tiers and a stair step structure. The stair step structure is positioned between first and second portions of the memory array and includes contact regions for respective conductive tiers of the stack of conductive tiers. The first portion of the memory array includes a first plurality of select gates extending in a particular direction over the stack. The second portion of the memory array includes a second plurality of select gates also extending in the particular direction over the stack of conductive tiers. Methods of forming and methods of operating such semiconductor devices, including vertical memory devices, are also disclosed.

公开(公告)号：US09082772B2

公开(公告)日：2015-07-14

申请号：US14085361

申请日：2013-11-20

Applicant: Micron Technology, Inc.

Inventor： Chang Wan Ha ,  Graham R. Wolstenholme ,  Deepak Thimmegowda

IPC: H01L29/76 ,  H01L29/788 ,  H01L23/552 ,  H01L23/535 ,  H01L21/033 ,  H01L21/3213 ,  H01L27/115

CPC classification number: H01L21/76816 ,  H01L21/0337 ,  H01L21/32139 ,  H01L21/76822 ,  H01L21/76865 ,  H01L23/535 ,  H01L27/1052 ,  H01L27/11519 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Apparatuses and methods for stair step formation using at least two masks, such as in a memory device, are provided. One example method can include forming a first mask over a conductive material to define a first exposed area, and forming a second mask over a portion of the first exposed area to define a second exposed area, the second exposed area is less than the first exposed area. Conductive material is removed from the second exposed area. An initial first dimension of the second mask is less than a first dimension of the first exposed area and an initial second dimension of the second mask is at least a second dimension of the first exposed area plus a distance equal to a difference between the initial first dimension of the second mask and a final first dimension of the second mask after a stair step structure is formed.

Abstract translation: 提供了使用至少两个掩模（例如存储器件）中的阶梯形成的装置和方法。 一个示例性方法可以包括在导电材料上形成第一掩模以限定第一暴露区域，以及在第一暴露区域的一部分上形成第二掩模以限定第二暴露区域，第二暴露区域小于第一暴露区域 区。 从第二暴露区域去除导电材料。 第二掩模的初始第一尺寸小于第一曝光区域的第一尺寸，并且第二掩模的初始第二尺寸是第一曝光区域的至少第二尺寸加上等于初始第一曝光区域之间的差距的距离 在形成阶梯结构之后，第二掩模的尺寸和第二掩模的最终第一尺寸。

公开(公告)号：US20140233318A1

公开(公告)日：2014-08-21

申请号：US14262308

申请日：2014-04-25

Applicant: Micron Technology, Inc.

Inventor： Chang Wan Ha

IPC: G11C16/10

CPC classification number: G06F12/0875 ,  G06F12/0246 ,  G06F12/0893 ,  G06F2212/2022 ,  G06F2212/3042 ,  G06F2212/452 ,  G06F2212/7203 ,  G11C8/10 ,  G11C16/0425 ,  G11C16/0433 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3454

Abstract: Examples described include dynamic data caches (DDCs), decoders and decoding methods that may fit into a smaller width area. The DDCs, decoders and decoding method may be used in flash memory devices. A single column select line may be provided to select a plurality of cached bytes, while a second select line selects a byte of the selected plurality. The column select line may be routed parallel to bit lines carrying data, while the second select line may be routed perpendicular to the bit lines.

Abstract translation: 所描述的示例包括可适应于较小宽度区域的动态数据高速缓存（DDC），解码器和解码方法。 DDC，解码器和解码方法可用于闪存设备。 可以提供单列选择线来选择多个缓存字节，而第二选择线选择所选择的多个字节。 列选择线可以平行于承载数据的位线被路由，而第二选择线可以垂直于位线被路由。

公开(公告)号：US08656092B2

公开(公告)日：2014-02-18

申请号：US13762874

申请日：2013-02-08

Applicant: Micron Technology, Inc.

Inventor： Chang Wan Ha

IPC: G06F12/00 ,  G06F13/00

CPC classification number: G06F12/0246 ,  G11C11/5642 ,  G11C16/0483 ,  G11C2211/5641 ,  G11C2211/5643 ,  G11C2211/5646

Abstract: A non-volatile memory device has a memory array comprising a plurality of memory cells. The array can operate in either a multilevel cell or single level cell mode and each cell has a lower page and an upper page of data. The memory device has a data latch for storing flag data and a cache latch coupled to the data latch. A read method comprises initiating a lower page read of a memory cell and reading, from the data latch, flag data that indicates whether a lower page read operation is necessary.

Abstract translation: 非易失性存储器件具有包括多个存储器单元的存储器阵列。 阵列可以在多电平单元或单电平单元模式下工作，并且每个单元都具有较低的页面和较高的数据页面。 存储器件具有用于存储标志数据的数据锁存器和耦合到数据锁存器的高速缓存锁存器。 读取方法包括启动存储器单元的下页读取并从数据锁存器读取指示是否需要下页读取操作的标志数据。

公开(公告)号：US09912498B2

公开(公告)日：2018-03-06

申请号：US14639293

申请日：2015-03-05

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Qiang Tang ,  Xiaojiang Guo ,  Chang Wan Ha

IPC: G11C7/00 ,  H04L25/02 ,  G06F13/40 ,  G11C5/04 ,  G11C29/02 ,  G11C29/50

CPC classification number: H04L25/0278 ,  G06F13/4086 ,  G11C5/04 ,  G11C29/025 ,  G11C29/028 ,  G11C29/50008

Abstract: Methods of operating integrated circuit devices are useful in testing impedance adjustment. Methods include connecting a node of the integrated circuit device to a first voltage node through a reference resistance and connecting the node to a second voltage node through a termination device, and comparing a voltage level at the node to a reference voltage for at least one resistance value of the termination device. When no available resistance value of the termination device generates a voltage level at the node that is deemed to match the reference voltage, the voltage level of the reference voltage may be altered, and the voltage level at the node may be compared to the altered reference voltage. When the voltage level at the node is deemed to match the altered reference voltage, the termination device may be deemed as passed. Otherwise, the termination device may be deemed as failed.