Invention Grant
- Patent Title: Binary translation mechanism
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Application No.: US14574797Application Date: 2014-12-18
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Publication No.: US09665374B2Publication Date: 2017-05-30
- Inventor: Koichi Yamada , Ashish Bijlani , Jiwei Lu , Cheng Yan Zhao
- Applicant: Koichi Yamada , Ashish Bijlani , Jiwei Lu , Cheng Yan Zhao
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Blakely Sokoloff Taylor & Zafman LLP
- Main IPC: G06F7/38
- IPC: G06F7/38 ; G06F13/00 ; G06F9/38 ; G06F9/30

Abstract:
A method is described. The method includes receiving an instruction, accessing a return cache to load a predicted return target address upon determining that the instruction is a return instruction, searching a lookup table for executable binary code upon determining that the predicted translated return target address is incorrect and executing the executable binary code to perform a binary translation.
Public/Granted literature
- US20160179547A1 Binary Translation Mechanism Public/Granted day:2016-06-23
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