Invention Grant
- Patent Title: Collision detection systems for detecting read-write collisions in memory systems after word line activation, and related systems and methods
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Application No.: US14857512Application Date: 2015-09-17
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Publication No.: US09666269B2Publication Date: 2017-05-30
- Inventor: Harish Shankar , Manish Garg , Joshua Lance Puckett , Rahul Krishnakumar Nadkarni
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agency: Withrow & Terranova, PLLC
- Main IPC: G11C11/00
- IPC: G11C11/00 ; G11C11/419 ; G11C7/10 ; G11C8/16

Abstract:
Collision detection systems for detecting read-write collisions in memory systems after word line activation are disclosed. In one aspect, a collision detection system is provided. The collision detection system includes a collision detection circuit for each bit cell row of memory array. Each collision detection circuit is configured to receive a write and read word line signal corresponding to the bit cell row. The collision detection circuit is configured to detect a write and read word line signal pair being active for a write and read operation for the same bit cell row. The collision detection circuit is configured to generate a collision detection signal to notify clients associated with the memory system that a read-write collision occurred. Detecting the read-write collisions after read word line activation reduces or avoids overhead delays in the read path, as opposed to detecting read-write collisions prior to activation of the read word line.
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