公开(公告)号：US10128845B2

公开(公告)日：2018-11-13

申请号：US15270174

申请日：2016-09-20

Applicant: QUALCOMM Incorporated

Inventor： Manish Garg

IPC: G11C7/00 ,  H03K19/00 ,  G11C5/14 ,  G11C7/06 ,  G11C7/12 ,  G11C8/08 ,  H03K19/0185

Abstract: Voltage level shifter (VLS) circuits employing a pre-conditioning circuit for pre-conditioning an input signal to be voltage level shifted in response to a pre-charge phase are disclosed. A VLS circuit is configured to voltage level shift an input signal in a lower voltage domain on an output node in a higher voltage domain. The VLS circuit includes a pre-charge circuit configured to pre-charge the output node in a pre-charge phase. The VLS circuit also includes a pull-up circuit and a pull-down circuit that are configured to pull-up and pull-down the pre-charge phase of the output node, respectively, in an evaluation phase based on a logic state of the input signal to generate the output signal. To mitigate or avoid contention between the pull-up and pull-down circuits in the evaluation phase, the input signal is pre-conditioned such that the pull-down circuit is deactivated in response to the pre-charge phase.

公开(公告)号：US09666269B2

公开(公告)日：2017-05-30

申请号：US14857512

申请日：2015-09-17

Applicant: QUALCOMM Incorporated

Inventor： Harish Shankar ,  Manish Garg ,  Joshua Lance Puckett ,  Rahul Krishnakumar Nadkarni

IPC: G11C11/00 ,  G11C11/419 ,  G11C7/10 ,  G11C8/16

CPC classification number: G11C11/419 ,  G11C7/1075 ,  G11C8/16

Abstract: Collision detection systems for detecting read-write collisions in memory systems after word line activation are disclosed. In one aspect, a collision detection system is provided. The collision detection system includes a collision detection circuit for each bit cell row of memory array. Each collision detection circuit is configured to receive a write and read word line signal corresponding to the bit cell row. The collision detection circuit is configured to detect a write and read word line signal pair being active for a write and read operation for the same bit cell row. The collision detection circuit is configured to generate a collision detection signal to notify clients associated with the memory system that a read-write collision occurred. Detecting the read-write collisions after read word line activation reduces or avoids overhead delays in the read path, as opposed to detecting read-write collisions prior to activation of the read word line.

公开(公告)号：US20160308372A1

公开(公告)日：2016-10-20

申请号：US15130549

申请日：2016-04-15

Applicant: QUALCOMM Incorporated

Inventor： Yeshwant Nagaraj Kolla ,  Neel Shashank Natekar ,  Manish Garg

IPC: H02J4/00

CPC classification number: H02J4/00 ,  G06F1/263 ,  G06F1/3296 ,  G11C5/14 ,  Y02D10/171

Abstract: Power rail control systems that include power multiplexing circuits that include cross-current conduction protection are disclosed. Power multiplexing circuit includes supply selection circuits each coupled between a respective supply power rail and an output power rail coupled to a powered circuit. To maintain power to the powered circuit during switching coupling of the output power rail, but while also avoiding current cross-conduction path between supply power rails, diode drop control circuits are provided in supply selection circuits. In diode drop operation mode, the diode drop control circuit associated with a higher voltage supply power rail is configured to regulate voltage supplied by such supply power rail to the output power rail to power the powered circuit. A current cross-conduction path is not created, because diode drop control circuits associated with lower voltage supply power rails are reverse biased to prevent current from flowing through their associated supply selection circuits.

Abstract translation: 公开了包括交叉电流传导保护的功率复用电路的电力轨控系统。 功率复用电路包括电源选择电路，每个电源选择电路分别耦合在相应的供电电源轨和耦合到电源电路的输出电源轨之间。 为了在输出电源轨的开关耦合期间维持供电电路的电力，但是在避免电源电源轨之间的电流交叉导通路径的同时，在电源选择电路中提供二极管降压控制电路。 在二极管降压操作模式中，与更高电压电源轨相关联的二极管降压控制电路被配置为将由这样的供电电源轨提供的电压调节到输出电源轨，以给供电电路供电。 不产生电流交叉导通路径，因为与低电压电源电源轨相关联的二极管降压控制电路被反向偏置以防止电流流过其相关联的电源选择电路。

公开(公告)号：US12271303B2

公开(公告)日：2025-04-08

申请号：US18349206

申请日：2023-07-10

Applicant: QUALCOMM Incorporated

Inventor： Manish Garg ,  Pratibind Kumar Jha ,  Prakhar Srivastava ,  Santhosh Reddy Akavaram

IPC: G06F12/02

Abstract: Methods that may be performed by a host controller and a memory controller of a computing device. The method synchronizes memory tables between the storage device and a host device by modifying an indicator in a first memory table on the storage device in response to a change in a memory mapping, the first memory table mapping logical addresses to physical addresses of memory on the storage device, the indicator identifying one or more address mapping changes of the first memory table, notifying the host device that the first memory table has been modified, and transmitting to the host device at least a portion of the first memory table including the one or more address mapping changes. The storage device processes memory requests from the host device based on one or more addresses affected by the one or more address mapping changes.

公开(公告)号：US09960759B2

公开(公告)日：2018-05-01

申请号：US14860713

申请日：2015-09-22

Applicant: QUALCOMM Incorporated

Inventor： Manish Garg ,  Ramasamy Adaikkalavan

IPC: G06F12/08 ,  G06F7/02 ,  H03K5/24 ,  H03K19/20 ,  G06F12/0802

CPC classification number: H03K5/24 ,  G06F7/026 ,  G06F12/0802 ,  G06F2212/60 ,  H03K19/20

Abstract: Disclosed systems and methods relate to comparison of a first number and a second number. A comparator receives first and second single-ended inputs (i.e., not represented in differential format), which may be n-bits wide, wherein the first input is an inverted version of the first number and the second input is a true version of the second number. A partial match circuit is implemented to generate a partial match output based only on the first single-ended input and the second single-ended input. A partial mismatch circuit is implemented to generate a partial mismatch output based only on the first single-ended input and the second single-ended input. A comparison output circuit is implemented to generate a comparison output of the first and second numbers based on the partial match output and the partial mismatch output.

公开(公告)号：US20180083625A1

公开(公告)日：2018-03-22

申请号：US15270174

申请日：2016-09-20

Applicant: QUALCOMM Incorporated

Inventor： Manish Garg

IPC: H03K19/00 ,  H03K19/0185 ,  G11C7/12 ,  G11C5/14 ,  G11C8/08 ,  G11C7/06

CPC classification number: H03K19/0013 ,  G11C5/147 ,  G11C7/06 ,  G11C7/12 ,  G11C8/08 ,  H03K19/018507 ,  H03K19/018521 ,  H03K19/018571

Abstract: Voltage level shifter (VLS) circuits employing a pre-conditioning circuit for pre-conditioning an input signal to be voltage level shifted in response to a pre-charge phase are disclosed. A VLS circuit is configured to voltage level shift an input signal in a lower voltage domain on an output node in a higher voltage domain. The VLS circuit includes a pre-charge circuit configured to pre-charge the output node in a pre-charge phase. The VLS circuit also includes a pull-up circuit and a pull-down circuit that are configured to pull-up and pull-down the pre-charge phase of the output node, respectively, in an evaluation phase based on a logic state of the input signal to generate the output signal. To mitigate or avoid contention between the pull-up and pull-down circuits in the evaluation phase, the input signal is pre-conditioned such that the pull-down circuit is deactivated in response to the pre-charge phase.

公开(公告)号：US09870818B1

公开(公告)日：2018-01-16

申请号：US15429842

申请日：2017-02-10

Applicant: QUALCOMM Incorporated

Inventor： Manish Garg

IPC: G11C8/10 ,  G11C11/419 ,  G11C11/418

CPC classification number: G11C11/419 ,  G11C7/1015 ,  G11C8/08 ,  G11C8/10 ,  G11C11/418 ,  G11C2207/2209

Abstract: Memory systems that provide separate read and write address decoding to support simultaneous memory read and write operations are disclosed. Separating read and write address decoding can avoid circuit conflicts for a simultaneous memory read and write operation even if employing single port memory bit cells. The read and write addresses of respective read and write operations are separately decoded into read and write row and column selects driven to a memory array so that simultaneous read and write operations are not affected by each other. To avoid a circuit conflict for a simultaneous read and write operation, the memory system is configured to prioritize a write row select over a read row select to drive a row of memory bit cells in the memory array. In this manner, that write operation will always be successful regardless of whether the read and write row select are to the same row.

公开(公告)号：US09768779B2

公开(公告)日：2017-09-19

申请号：US14731747

申请日：2015-06-05

Applicant: QUALCOMM Incorporated

Inventor： Rahul Krishnakumar Nadkarni ,  Stephen Edward Liles ,  Manish Garg

IPC: H03K19/173 ,  H03K19/094 ,  H03K19/0185 ,  H03K3/012 ,  H03K3/356

CPC classification number: H03K19/018521 ,  H03K3/012 ,  H03K3/356165

Abstract: Voltage level shifters employing preconditioning circuits are disclosed. Related systems and methods are also disclosed. In one aspect, voltage level shifter is configured to generate a voltage level shifted non-complement output signal and complement output signal corresponding to non-complement input signal and complement input signal, respectively. First pull-up circuit is configured to generate complement output signal in response to non-complement input signal transitioning to logic low voltage. First pull-down circuit is configured to generate non-complement output signal in response to complement input signal transitioning to logic high voltage. First preconditioning circuit is configured to receive non-complement and complement output signals and generate and provide shifted voltage signal to complement output in response to non-complement output signal transitioning to logic low voltage. This allows the complement output signal to transition to the shifted voltage more quickly.

公开(公告)号：US10541044B2

公开(公告)日：2020-01-21

申请号：US15642451

申请日：2017-07-06

Applicant: QUALCOMM Incorporated

Inventor： Thomas Philip Speier ,  Viren Ramesh Patel ,  Michael Phan ,  Manish Garg ,  Kevin Magill ,  Paul Steinmetz ,  Clint Mumford ,  Kshitiz Saxena

IPC: G11C29/44 ,  G06F11/07 ,  G11C29/00

Abstract: Providing efficient handling of memory array failures in processor-based systems is disclosed. In this regard, in one aspect, a memory controller of a processor-based device is configured to detect a defect within a memory element of a plurality of memory elements of a memory array. In response, a disable register of one or more disable registers is set to correspond to the memory element to indicate that the memory element is disabled. The memory controller receives a memory access request to a memory address corresponding to the memory element, and determines, based on one or more disable registers, whether the memory element is disabled. If so, the memory controller disallows the memory access request. Some aspects may provide that the memory controller, in response to detecting the defect, provides a failure indication to an executing process, and subsequently receives, from the executing process, a request to set the disable register.

公开(公告)号：US10171080B2

公开(公告)日：2019-01-01

申请号：US15270174

申请日：2016-09-20

Applicant: QUALCOMM Incorporated

Inventor： Manish Garg

IPC: G11C7/00 ,  H03K19/00 ,  G11C5/14 ,  G11C7/06 ,  G11C7/12 ,  G11C8/08 ,  H03K19/0185

Abstract: Voltage level shifter (VLS) circuits employing a pre-conditioning circuit for pre-conditioning an input signal to be voltage level shifted in response to a pre-charge phase are disclosed. A VLS circuit is configured to voltage level shift an input signal in a lower voltage domain on an output node in a higher voltage domain. The VLS circuit includes a pre-charge circuit configured to pre-charge the output node in a pre-charge phase. The VLS circuit also includes a pull-up circuit and a pull-down circuit that are configured to pull-up and pull-down the pre-charge phase of the output node, respectively, in an evaluation phase based on a logic state of the input signal to generate the output signal. To mitigate or avoid contention between the pull-up and pull-down circuits in the evaluation phase, the input signal is pre-conditioned such that the pull-down circuit is deactivated in response to the pre-charge phase.