A memory device includes a substrate having common source regions thereon, common source lines extending along a surface of the substrate and contacting the common source regions, respectively, and channel structures extending away from the surface of the substrate between the common source lines. The common source lines define a unit cell of the memory device therebetween. The memory device further includes an electrode stack structure having interlayer insulating layers and conductive electrode layers that are alternately stacked along sidewalls of the channel structures. The conductive electrode layers define respective gates of selection transistors and memory cell transistors of the memory device. An isolation insulating layer, which includes a portion of a sacrificial layer, is disposed between adjacent ones of the interlayer insulating layers in the stack structure. The isolation insulating layer divides at least one of the conductive electrode layers in the stack structure into electrically separate portions.