发明授权
- 专利标题： Split well zero threshold voltage field effect transistor for integrated circuits
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申请号： US14217691申请日： 2014-03-18
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公开(公告)号： US09666717B2公开(公告)日： 2017-05-30
- 发明人: Jagar Singh , Konstantin G. Korablev , Andy Chih-Hung Wei
- 申请人： GLOBALFOUNDRIES Inc.
- 申请人地址： KY Grand Cayman
- 专利权人： GLOBAL FOUNDRIES, INC.
- 当前专利权人： GLOBAL FOUNDRIES, INC.
- 当前专利权人地址： KY Grand Cayman
- 代理机构： Williams Morgan, P.C.
- 主分类号： H01L29/40
- IPC分类号： H01L29/40 ; H01L29/78 ; H01L29/417 ; H01L29/66 ; H01L29/36 ; H01L21/265
摘要：
Approaches for altering the threshold voltage (e.g., to zero threshold voltage) in a fin-type field effect transistor (FinFET) device are provided. In embodiments of the invention, a first N+ region and a second N+ region are formed on a finned substrate that has a p-well construction. A region of the finned substrate located between the first N+ region and the second N+ region is doped with a negative implant species to form an n-well. The size and/or composition of this n-well region can be adjusted in view of the existing p-well construction of the substrate device to change the threshold voltage of the FinFET device (e.g., to yield a zero threshold voltage FinFET device).
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