Invention Grant
- Patent Title: Split well zero threshold voltage field effect transistor for integrated circuits
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Application No.: US14217691Application Date: 2014-03-18
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Publication No.: US09666717B2Publication Date: 2017-05-30
- Inventor: Jagar Singh , Konstantin G. Korablev , Andy Chih-Hung Wei
- Applicant: GLOBALFOUNDRIES Inc.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBAL FOUNDRIES, INC.
- Current Assignee: GLOBAL FOUNDRIES, INC.
- Current Assignee Address: KY Grand Cayman
- Agency: Williams Morgan, P.C.
- Main IPC: H01L29/40
- IPC: H01L29/40 ; H01L29/78 ; H01L29/417 ; H01L29/66 ; H01L29/36 ; H01L21/265

Abstract:
Approaches for altering the threshold voltage (e.g., to zero threshold voltage) in a fin-type field effect transistor (FinFET) device are provided. In embodiments of the invention, a first N+ region and a second N+ region are formed on a finned substrate that has a p-well construction. A region of the finned substrate located between the first N+ region and the second N+ region is doped with a negative implant species to form an n-well. The size and/or composition of this n-well region can be adjusted in view of the existing p-well construction of the substrate device to change the threshold voltage of the FinFET device (e.g., to yield a zero threshold voltage FinFET device).
Public/Granted literature
- US20150270400A1 SPLIT WELL ZERO THRESHOLD VOLTAGE FIELD EFFECT TRANSISTOR FOR INTEGRATED CIRCUITS Public/Granted day:2015-09-24
Information query
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