Invention Grant
- Patent Title: Method and apparatus for reducing read latency for a block erasable non-volatile memory
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Application No.: US14752817Application Date: 2015-06-26
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Publication No.: US09679658B2Publication Date: 2017-06-13
- Inventor: David J. Pelster , Yogesh B. Wakchaure , Xin Guo , Paul D. Ruby , Justin R. Dayacap , Joseph F. Doller , Robert E. Frickey
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: US CA Santa Clara
- Agency: Konrad Raynes Davda & Victor LLP
- Agent David W. Victor
- Main IPC: G11C11/34
- IPC: G11C11/34 ; G11C16/16 ; G11C16/26 ; G11C16/34

Abstract:
Provided are an apparatus, memory controller and method for performing a block erase operation with respect to a non-volatile memory. A command is generated to perform a portion of the block erase operation. At least one read or write operation is performed after executing the command. An additional instance of the command is executed in response to determining that the block erase operation did not complete after performing the at least one read or write operation.
Public/Granted literature
- US20160379715A1 METHOD AND APPARATUS FOR REDUCING READ LATENCY FOR A BLOCK ERASABLE NON-VOLATILE MEMORY Public/Granted day:2016-12-29
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