- 专利标题: Signal reconstruction in sequential logic circuitry
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申请号: US14882414申请日: 2015-10-13
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公开(公告)号: US09684746B2公开(公告)日: 2017-06-20
- 发明人: Parijat Biswas , Shyam Datta , Subhrajyoti Chakraborty , Minakshi Chakravorty
- 申请人: Synopsys, Inc.
- 申请人地址: US CA Mountain View
- 专利权人: Synopsys, Inc.
- 当前专利权人: Synopsys, Inc.
- 当前专利权人地址: US CA Mountain View
- 代理机构: Fenwick & West LLP
- 主分类号: G06F17/50
- IPC分类号: G06F17/50
摘要:
A method for reconstructing at least one output signal associated to a sequential logic circuitry block of a circuit is disclosed. At least one input signal is associated to the sequential logic circuitry block. The method comprises simulating a value of the at least one output signal depending on the at least one input signal and determining a transfer function for computing the value of the output signal directly after the simulation timestamp depending on the input signal and/or on the value of the output signal directly before the simulation timestamp. The method further comprises computing the value of the at least one output signal directly after the simulation timestamp as a function value of the transfer function, if a reconstruction condition is fulfilled.
公开/授权文献
- US20170103152A1 Signal Reconstruction in Sequential Logic Circuitry 公开/授权日:2017-04-13
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