公开(公告)号：US09684746B2

公开(公告)日：2017-06-20

申请号：US14882414

申请日：2015-10-13

申请人： Synopsys, Inc.

发明人： Parijat Biswas ,  Shyam Datta ,  Subhrajyoti Chakraborty ,  Minakshi Chakravorty

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： A method for reconstructing at least one output signal associated to a sequential logic circuitry block of a circuit is disclosed. At least one input signal is associated to the sequential logic circuitry block. The method comprises simulating a value of the at least one output signal depending on the at least one input signal and determining a transfer function for computing the value of the output signal directly after the simulation timestamp depending on the input signal and/or on the value of the output signal directly before the simulation timestamp. The method further comprises computing the value of the at least one output signal directly after the simulation timestamp as a function value of the transfer function, if a reconstruction condition is fulfilled.

公开(公告)号：US20220108056A1

公开(公告)日：2022-04-07

申请号：US17490700

申请日：2021-09-30

申请人： Synopsys, Inc.

发明人： Parijat Biswas ,  Minakshi Chakravorty ,  Sitikant Sahu

IPC分类号： G06F30/323

摘要： Hardware description language (HDL) code for an integrated circuit (IC) design may be parsed to obtain an IC design parse tree. A transformation pattern may include a first pattern and a second pattern. The transformation pattern may be parsed to obtain a transformation pattern parse tree. The IC design parse tree and the transformation pattern parse tree may be used to identify a portion of the HDL code that matches the first pattern. The identified portion of the HDL code may be transformed based on the second pattern to obtain a transformed portion of the HDL code. The portion of the HDL code may be replaced by the transformed portion of the HDL code.

公开(公告)号：US20170103152A1

公开(公告)日：2017-04-13

申请号：US14882414

申请日：2015-10-13

申请人： Synopsys, Inc.

发明人： Parijat Biswas ,  Shyam Datta ,  Subhrajyoti Chakraborty ,  Minakshi Chakravorty

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： A method for reconstructing at least one output signal associated to a sequential logic circuitry block of a circuit is disclosed. At least one input signal is associated to the sequential logic circuitry block. The method comprises simulating a value of the at least one output signal depending on the at least one input signal and determining a transfer function for computing the value of the output signal directly after the simulation timestamp depending on the input signal and/or on the value of the output signal directly before the simulation timestamp. The method further comprises computing the value of the at least one output signal directly after the simulation timestamp as a function value of the transfer function, if a reconstruction condition is fulfilled.

公开(公告)号：US11853665B2

公开(公告)日：2023-12-26

申请号：US17490700

申请日：2021-09-30

申请人： Synopsys, Inc.

发明人： Parijat Biswas ,  Minakshi Chakravorty ,  Sitikant Sahu

IPC分类号： G06F30/323

CPC分类号： G06F30/323

摘要： Hardware description language (HDL) code for an integrated circuit (IC) design may be parsed to obtain an IC design parse tree. A transformation pattern may include a first pattern and a second pattern. The transformation pattern may be parsed to obtain a transformation pattern parse tree. The IC design parse tree and the transformation pattern parse tree may be used to identify a portion of the HDL code that matches the first pattern. The identified portion of the HDL code may be transformed based on the second pattern to obtain a transformed portion of the HDL code. The portion of the HDL code may be replaced by the transformed portion of the HDL code.

公开(公告)号：US10521528B2

公开(公告)日：2019-12-31

申请号：US15597065

申请日：2017-05-16

申请人： Synopsys, Inc.

发明人： Parijat Biswas ,  Shyam Datta ,  Subhrajyoti Chakraborty ,  Minakshi Chakravorty

IPC分类号： G06F17/50

摘要： A method for reconstructing at least one output signal associated to a sequential logic circuitry block of a circuit is disclosed. At least one input signal is associated to the sequential logic circuitry block. The method comprises determining a value of the at least one output signal depending on the at least one input signal and determining a transfer function for computing the value of the output signal directly after a timestamp depending on the input signal and/or on the value of the output signal directly before the timestamp. The method further comprises computing the value of the at least one output signal directly after the timestamp as a function value of the transfer function, if a reconstruction condition is fulfilled.

公开(公告)号：US20170255726A1

公开(公告)日：2017-09-07

申请号：US15597065

申请日：2017-05-16

申请人： Synopsys, Inc.

发明人： Parijat Biswas ,  Shyam Datta ,  Subhrajyoti Chakraborty ,  Minakshi Chakravorty

IPC分类号： G06F17/50

摘要： A method for reconstructing at least one output signal associated to a sequential logic circuitry block of a circuit is disclosed. At least one input signal is associated to the sequential logic circuitry block. The method comprises determining a value of the at least one output signal depending on the at least one input signal and determining a transfer function for computing the value of the output signal directly after a timestamp depending on the input signal and/or on the value of the output signal directly before the timestamp. The method further comprises computing the value of the at least one output signal directly after the timestamp as a function value of the transfer function, if a reconstruction condition is fulfilled.