Invention Grant
- Patent Title: Interconnect wires including relatively low resistivity cores
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Application No.: US15096609Application Date: 2016-04-12
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Publication No.: US09691657B2Publication Date: 2017-06-27
- Inventor: Hui Jae Yoo , Tejaswi K. Indukuri , Ramanan V. Chebiam , James S. Clarke
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Grossman, Tucker, Perreault & Pfleger, PLLC
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L23/52 ; H01L29/40 ; H01L21/768 ; H01L23/532
Abstract:
A dielectric layer and a method of forming thereof. An opening defined in a dielectric layer and a wire deposited within the opening, wherein the wire includes a core material surrounded by a jacket material, wherein the jacket material exhibits a first resistivity ρ1 and the core material exhibits a second resistivity ρ2 and ρ2 is less than ρ1.
Public/Granted literature
- US20160225665A1 INTERCONNECT WIRES INCLUDING RELATIVELY LOW RESISTIVITY CORES Public/Granted day:2016-08-04
Information query
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