Invention Grant
- Patent Title: Methods and structures for packaging semiconductor dies
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Application No.: US14165280Application Date: 2014-01-27
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Publication No.: US09698121B2Publication Date: 2017-07-04
- Inventor: Yi-Chao Mao , Jing-Cheng Lin
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater Matsil, LLP
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L21/56

Abstract:
A method of packaging a semiconductor device, comprising: attaching a plurality of dies to a carrier wafer, wherein each of the dies includes a top surface; forming a molding compound layer over the dies, wherein the top surface of the dies are covered by the molding compound layer; removing a first portion of the molding compound layer; removing a second portion of the molding compound layer such that the top surface of the dies is not covered by the molding compound layer; forming a redistribution layer (RDL) over the top surface of the dies; forming a plurality of solder balls over at least a portion of the RDL; and singulating the dies.
Public/Granted literature
- US20150214186A1 Methods and Structures for Packaging Semiconductor Dies Public/Granted day:2015-07-30
Information query
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