Invention Grant
- Patent Title: Control transfer termination instructions of an instruction set architecture (ISA)
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Application No.: US13690221Application Date: 2012-11-30
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Publication No.: US09703567B2Publication Date: 2017-07-11
- Inventor: Vedvyas Shanbhogue , Jason W. Brandt , Uday R. Savagaonkar , Ravi L. Sahita
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Trop, Pruner & Hu, P.C.
- Main IPC: G06F9/30
- IPC: G06F9/30 ; G06F9/38 ; G06F21/52
Abstract:
In an embodiment, the present invention includes a processor having an execution logic to execute instructions and a control transfer termination (CTT) logic coupled to the execution logic. This logic is to cause a CTT fault to be raised if a target instruction of a control transfer instruction is not a CTT instruction. Other embodiments are described and claimed.
Public/Granted literature
- US20140156972A1 Control Transfer Termination Instructions Of An Instruction Set Architecture (ISA) Public/Granted day:2014-06-05
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