Invention Grant
- Patent Title: Reduction of defects in wafer level chip scale package (WLCSP) devices
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Application No.: US14927283Application Date: 2015-10-29
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Publication No.: US09704823B2Publication Date: 2017-07-11
- Inventor: Tonny Kamphuis , Roelf Anco Jacob Groenhuis , Leonardus Antonius Elisabeth van Gemert , Caroline Catharina Maria Beelen-Hendrikx , Jetse de Witte , Franciscus Henrikus Martinus Swartjes
- Applicant: NXP B.V.
- Applicant Address: NL Eindhoven
- Assignee: NXP B.V.
- Current Assignee: NXP B.V.
- Current Assignee Address: NL Eindhoven
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L23/00 ; H01L23/31 ; H01L21/56 ; H01L21/78 ; H01L21/683 ; H01L23/544

Abstract:
Consistent with example embodiments, a wafer substrate undergoes processing in which a resilient material is applied to the front-side and back-side surfaces of the wafer substrate. By defining trenches in saw lanes between active device die, additional resilient material may be placed therein. In an example embodiment, after the active device die are separated into individual product devices, the resulting product device has coverage on the front-side surface, back-side surface, and the four vertical faces of the encapsulated active device die. The front-side surface has exposed contact areas so that the product device may be attached to an end user's system circuit board. Further, the resilient coating protects the encapsulated active device die from damage during assembly.
Public/Granted literature
- US20160276176A1 REDUCTION OF DEFECTS IN WAFER LEVEL CHIP SCALE PACKAGE (WLCSP) DEVICES Public/Granted day:2016-09-22
Information query
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