A display panel includes: a pixel electrode comprising first, second, and third sub-pixel electrodes that are separated from each other; a first thin film transistor connected to the first sub-pixel electrode; second and fourth thin film transistors connected to the second sub-pixel electrode; third and fifth thin film transistors connected to the third sub-pixel electrode; a first gate line connected to the first to fourth thin film transistors; a second gate line connected to the fifth thin film transistor; a data line insulated from and intersecting the first and second gate lines and connected to the first to third thin film transistors; a first storage electrode line disposed adjacent to the first gate line; and a second storage electrode line disposed adjacent to the second gate line.